Packaging information
| Package | Pins SOT-23-THN (DDF) | 8 |
| Operating temperature range (°C) -40 to 125 |
| Package qty | Carrier 3,000 | LARGE T&R |
Features for the TLC3555
- Very-low power consumption
- 1mW (typical) at VDD = 5V
- Astable operation up to 3MHz
- CMOS output capable of swinging rail to rail
- High-output-current capability
- Sink 200mA
- Source 50mA
- Output fully compatible with CMOS, TTL, and MOS logic
- Integrated RESET pullup to VDD
- Power-on reset to known state
- Integrated thermal shutdown protection
- Single-supply operation from 1.5V to 18V
Description for the TLC3555
The TLC3555 is a monolithic timing circuit fabricated using a TI CMOS process. The timer is fully compatible with CMOS, TTL, and MOS logic and operates at frequencies to 3MHz and even beyond. The TLC3555 improves upon the existing TLC555 from both a performance and feature standpoint, with tighter specification tolerances and additional features, such as thermal shutdown and power-on reset.
The trigger, threshold, and reset logic of the TLC3555 follow the same truth table as the TLC555. Set the reset pin (RESET) high for typical operation, or set the reset pin low to reset the flip-flop and force the output low. The TLC3555 features an internal pullup resistor from RESET to VDD, which can reduce passive count and save board area.
As a result of low propagation delay and rapid rise and fall times, the TLC3555 supports higher-frequency astable operation than previous timers such as the NE555 and TLC555. At a 15V supply, the TLC3555 achieves a clean square wave at 3.1MHz in TI’s conventional astable test circuit. When used as an oscillator, with the output and inputs tied together, the TLC3555 achieves an oscillatory frequency of 7.2MHz. Circuit parasitics dominate the response at high frequencies. In addition to the D package, which is pin-to-pin compatible with the TLC555, the TLC3555 is offered in a DDF package that enables concise implementations with reduced parasitics.