CD4028B

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CMOS decodificadores controladores BCD a decimal o Binario a octal

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Hoja de datos

document-pdfAcrobat CD4028B TYPES datasheet (Rev. C) (Inglés)

CD4028B

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Detalles del producto

Technology family

CD4000

Number of channels

1

Operating temperature range (°C)

-55 to 125

Rating

Catalog

Supply current (max) (µA)

3000

Technology family

CD4000

Number of channels

1

Operating temperature range (°C)

-55 to 125

Rating

Catalog

Supply current (max) (µA)

3000

SOIC (D)

16

59.4 mm² (9.9 mm × 6 mm)

TSSOP (PW)

16

32 mm² (5 mm × 6.4 mm)

PDIP (N)

16

181.42 mm² (19.3 mm × 9.4 mm)

SOP (NS)

16

79.56 mm² (10.2 mm × 7.8 mm)

BCD-to-decimal decoding or binary-to-octal decoding
High decoded output drive capability
"Positive logic" inputs and outputs……decoded outputs go high on selection
Medium-speed operation… t_PHL, t_PLH = 80 ns (typ.) @ V_DD = 10 V
Standardized, symmetrical output characteristics
100% tested for quiescent current at 20 V
Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
Noise margin (full package-temperature range) =
        1 V at V_DD = 5 V
        2 V at V_DD = 10 V
     2.5 V at V_DD = 15 V
5-V, 10-V, and 15-V parametric ratings
Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
Applications:
- Code conversion
- Indicator-tube decoder
- Address decoding-memory selection control

Data sheet acquired from Harris Semiconductor

BCD-to-decimal decoding or binary-to-octal decoding
High decoded output drive capability
"Positive logic" inputs and outputs……decoded outputs go high on selection
Medium-speed operation… t_PHL, t_PLH = 80 ns (typ.) @ V_DD = 10 V
Standardized, symmetrical output characteristics
100% tested for quiescent current at 20 V
Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
Noise margin (full package-temperature range) =
        1 V at V_DD = 5 V
        2 V at V_DD = 10 V
     2.5 V at V_DD = 15 V
5-V, 10-V, and 15-V parametric ratings
Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
Applications:
- Code conversion
- Indicator-tube decoder
- Address decoding-memory selection control

Data sheet acquired from Harris Semiconductor

CD4028 types are BCD-to-decimal or binary-to-octal decoders consisting of buffering on all 4 inputs, decoding-logic gates, and 10 output buffers. A BCD code applied to the four input, A to D, results in a high level at the selected one of 10 decimal decoded outputs. Similarly, a 3-bit binary code applied to inputs A through C is decoded in octal code at output 0 to 7 if D = "0". High drive capability is provided at all outputs to enhance dc and dynamic performance in high fan-out applications.

The CD4028B-Series types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

CD4028 types are BCD-to-decimal or binary-to-octal decoders consisting of buffering on all 4 inputs, decoding-logic gates, and 10 output buffers. A BCD code applied to the four input, A to D, results in a high level at the selected one of 10 decimal decoded outputs. Similarly, a 3-bit binary code applied to inputs A through C is decoded in octal code at output 0 to 7 if D = "0". High drive capability is provided at all outputs to enhance dc and dynamic performance in high fan-out applications.

The CD4028B-Series types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

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Documentación principal	Tipo	Título	Opciones de formato	Descargar la versión más reciente en inglés	Fecha
*	Hoja de datos	CD4028B TYPES datasheet (Rev. C)			14/10/2003

Diseño y desarrollo

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14-24-LOGIC-EVM — Módulo de evaluación genérico de productos lógicos para encapsulados D, DB, DGV, DW, DYY, NS y PW de

El módulo de evaluación (EVM) 14-24-LOGIC-EVM está diseñado para admitir cualquier dispositivo lógico que se encuentre en un encapsulado D, DW, DB, NS, PW, DYY o DGV de 14 a 24 pines.

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Encapsulado	Pines	Símbolos CAD, huellas y modelos 3D
SOIC (D)	16	Ultra Librarian
TSSOP (PW)	16	Ultra Librarian
PDIP (N)	16	Ultra Librarian
SOP (NS)	16	Ultra Librarian

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CD4028B

CMOS decodificadores controladores BCD a decimal o Binario a octal

CD4028B

Detalles del producto

Documentación técnica

Diseño y desarrollo

14-24-LOGIC-EVM — Módulo de evaluación genérico de productos lógicos para encapsulados D, DB, DGV, DW, DYY, NS y PW de

Pedidos y calidad

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