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Latches tipo D

CD4042B

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Cierre 'D' de reloj cuádruple CMOS

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Hoja de datos

CD4042B

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Detalles del producto

Number of channels 4 Technology family CD4000 Input type Standard CMOS Output type CMOS Clock frequency (max) (MHz) 8 IOL (max) (mA) 2.4 IOH (max) (mA) -2.4 Supply current (max) (µA) 600 Features High speed (tpd 10-50ns), Partial power down (Ioff), Standard speed (tpd > 50ns) Operating temperature range (°C) -55 to 125 Rating Catalog
Number of channels 4 Technology family CD4000 Input type Standard CMOS Output type CMOS Clock frequency (max) (MHz) 8 IOL (max) (mA) 2.4 IOH (max) (mA) -2.4 Supply current (max) (µA) 600 Features High speed (tpd 10-50ns), Partial power down (Ioff), Standard speed (tpd > 50ns) Operating temperature range (°C) -55 to 125 Rating Catalog
SOIC (DW) 16 106.09 mm² (10.3 mm × 10.3 mm) SOP (NS) 16 79.56 mm² (10.2 mm × 7.8 mm) SOIC (D) 16 59.4 mm² (9.9 mm × 6 mm) PDIP (N) 16 181.42 mm² (19.3 mm × 9.4 mm) TSSOP (PW) 16 32 mm² (5 mm × 6.4 mm)
  • Clock polarity control
  • Q and Q\ outputs
  • Common Clock
  • Low power TTL compatible
  • Standardized, symmetrical output characteristics
  • 100% tested for quiescent current at 20 V
  • Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
  • 5-V, 10-V, and 15-V parametric ratings
  • Noise margin (full package-temperature range) =
            1 V at VDD = 5 V
            2 V at VDD = 10 V
         2.5 V at VDD = 15 V
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
  • Applications:
    • Buffer storage
    • Holding register
    • General digital logic

Data sheet acquired from Harris Semiconductor
  • Clock polarity control
  • Q and Q\ outputs
  • Common Clock
  • Low power TTL compatible
  • Standardized, symmetrical output characteristics
  • 100% tested for quiescent current at 20 V
  • Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
  • 5-V, 10-V, and 15-V parametric ratings
  • Noise margin (full package-temperature range) =
            1 V at VDD = 5 V
            2 V at VDD = 10 V
         2.5 V at VDD = 15 V
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
  • Applications:
    • Buffer storage
    • Holding register
    • General digital logic

Data sheet acquired from Harris Semiconductor

CD4042B types contain four latch circuits, each strobed by a common clock. Complementary buffered outputs are available from each circuit. The impedance of the n- and p-channel output devices is balanced and all outputs are electrically identical.

Information present at the data input is transferred to outputs Q and Q\ during the CLOCK level which is programmed by the POLARITY input. For POLARITY = 0 the transfer occurs during the 0 CLOCK level and for POLARITY = 1 the transfer occurs during the 1 CLOCK level. The outputs follow the data input providing the CLOCK and POLARITY levels defined above are present. When a CLOCK transition occurs (positive for POLARITY = 0 and negative for POLARITY = 1) the information present at the input during the CLOCK transition is retained at the output until an opposite CLOCK transition occurs.

The CD4042B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffixes), 16-lead dual-in-line plastic package (E suffix), 16-lead small-outline packages (D, DR, DT, DW, DWR, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

CD4042B types contain four latch circuits, each strobed by a common clock. Complementary buffered outputs are available from each circuit. The impedance of the n- and p-channel output devices is balanced and all outputs are electrically identical.

Information present at the data input is transferred to outputs Q and Q\ during the CLOCK level which is programmed by the POLARITY input. For POLARITY = 0 the transfer occurs during the 0 CLOCK level and for POLARITY = 1 the transfer occurs during the 1 CLOCK level. The outputs follow the data input providing the CLOCK and POLARITY levels defined above are present. When a CLOCK transition occurs (positive for POLARITY = 0 and negative for POLARITY = 1) the information present at the input during the CLOCK transition is retained at the output until an opposite CLOCK transition occurs.

The CD4042B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffixes), 16-lead dual-in-line plastic package (E suffix), 16-lead small-outline packages (D, DR, DT, DW, DWR, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).
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Documentación técnica

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Documentación principal Tipo Título Opciones de formato Descargar la versión más reciente en inglés Fecha
* Hoja de datos CD4042B TYPES datasheet (Rev. D) 14/10/2003
Nota sobre la aplicación Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 15/12/2022

Diseño y desarrollo

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Placa de evaluación

14-24-LOGIC-EVM — Módulo de evaluación genérico de productos lógicos para encapsulados D, DB, DGV, DW, DYY, NS y PW de

El módulo de evaluación (EVM) 14-24-LOGIC-EVM está diseñado para admitir cualquier dispositivo lógico que se encuentre en un encapsulado D, DW, DB, NS, PW, DYY o DGV de 14 a 24 pines.

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Encapsulado Pines Símbolos CAD, huellas y modelos 3D
SOIC (DW) 16 Ultra Librarian
SOP (NS) 16 Ultra Librarian
SOIC (D) 16 Ultra Librarian
PDIP (N) 16 Ultra Librarian
TSSOP (PW) 16 Ultra Librarian
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