CD74HC4017

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Contador/divisor de décadas CMOS Logic de alta velocidad con 10 salidas decodificadas

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document-pdfAcrobat CD54HC4017/CD74HC4017 High-Speed CMOS Logic Decade Counter/Divider datasheet (Rev. D) (Inglés)

CD74HC4017

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Detalles del producto

Function

Counter

Bits (#)

10

Technology family

HC

Input type

Standard CMOS

Output type

Push-Pull

Features

Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode

Operating temperature range (°C)

-55 to 125

Rating

Catalog

Function

Counter

Bits (#)

10

Technology family

HC

Input type

Standard CMOS

Output type

Push-Pull

Features

Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode

Operating temperature range (°C)

-55 to 125

Rating

Catalog

SOIC (D)

16

59.4 mm² (9.9 mm × 6 mm)

TSSOP (PW)

16

32 mm² (5 mm × 6.4 mm)

PDIP (N)

16

181.42 mm² (19.3 mm × 9.4 mm)

SOP (NS)

16

79.56 mm² (10.2 mm × 7.8 mm)

Fully Static Operation
Buffered Inputs
Common Reset
Positive Edge Clocking
Typical f_MAX = 50MHz at V_CC =5V,C_L = 15pF, T_A =25°C
Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
Wide Operating Temperature Range . . . -55°C to 125°C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL Logic ICs
HC Types
- 2V to 6V Operation
- High Noise Immunity: N_IL = 30%, N_IH = 30% of V_CC at V_CC = 5V

Fully Static Operation
Buffered Inputs
Common Reset
Positive Edge Clocking
Typical f_MAX = 50MHz at V_CC =5V,C_L = 15pF, T_A =25°C
Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
Wide Operating Temperature Range . . . -55°C to 125°C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL Logic ICs
HC Types
- 2V to 6V Operation
- High Noise Immunity: N_IL = 30%, N_IH = 30% of V_CC at V_CC = 5V

The ’HC4017 is a high speed silicon gate CMOS 5-stage Johnson counter with 10 decoded outputs. Each of the decoded outputs is normally low and sequentially goes high on the low to high transition clock period of the 10 clock period cycle. The CARRY (TC) output transitions low to high after OUTPUT 10 goes low, and can be used in conjunction with the CLOCK ENABLE (CE\) to cascade several stages. The CLOCK ENABLE input disables counting when in the high state. A RESET (MR) input is also provided which when taken high sets all the decoded outputs, except "0", low.

The device can drive up to 10 low power Schottky equivalent loads.

The ’HC4017 is a high speed silicon gate CMOS 5-stage Johnson counter with 10 decoded outputs. Each of the decoded outputs is normally low and sequentially goes high on the low to high transition clock period of the 10 clock period cycle. The CARRY (TC) output transitions low to high after OUTPUT 10 goes low, and can be used in conjunction with the CLOCK ENABLE (CE\) to cascade several stages. The CLOCK ENABLE input disables counting when in the high state. A RESET (MR) input is also provided which when taken high sets all the decoded outputs, except "0", low.

The device can drive up to 10 low power Schottky equivalent loads.

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Documentación principal	Tipo	Título	Opciones de formato	Descargar la versión más reciente en inglés		Fecha
*	Hoja de datos	CD54HC4017/CD74HC4017 High-Speed CMOS Logic Decade Counter/Divider datasheet (Rev. D)			16/10/2003

CD74HC4017

Contador/divisor de décadas CMOS Logic de alta velocidad con 10 salidas decodificadas

CD74HC4017

Detalles del producto

Documentación técnica

Pedidos y calidad

Soporte y capacitación

Foros de TI E2E™ con asistencia técnica de los ingenieros de TI