SMJ320C6701

Name: SMJ320C6701
Brand: TI
SKU: SMJ320C6701
Price: 1608.46 USD

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DSP de punto flotante de calidad militar C67x: encapsulado cerámico

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Hoja de datos

document-pdfAcrobat Floating-Point Digital Signal Processor datasheet (Rev. A) (Inglés)

SMJ320C6701

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Detalles del producto

CPU

32-/64-bit

Frequency (MHz)

167

Rating

Military

Operating temperature range (°C)

-55 to 115

CPU

32-/64-bit

Frequency (MHz)

167

Rating

Military

Operating temperature range (°C)

-55 to 115

CFCBGA (GLP)

429

729 mm² 27 x 27

Highest Performance Floating-Point Digital
Signal Processor (DSP) SMJ320C6701
- 7-, 6-ns Instruction Cycle Time
- 140-, 167-MHz Clock Rate
- Eight 32-Bit Instructions/Cycle
- Up to 1 GFLOPS Performance
- Pin-Compatible With ’C6201 Fixed-Point DSP
SMJ: QML Processing to MIL-PRF-38535
SM: Standard Processing
Operating Temperature Ranges
- Extended (W) –55°C to 115°C
- Extended (S) –40°C to 90°C
VelociTI™ Advanced Very Long Instruction
Word (VLIW) ’C67x CPU Core
- Eight Highly Independent Functional Units:
  - Four ALUs (Floating- and Fixed-Point)
  - Two ALUs (Fixed-Point)
  - Two Multipliers (Floating- and
    Fixed-Point)
- Load-Store Architecture With 32 32-Bit
  General-Purpose Registers
- Instruction Packing Reduces Code Size
- All Instructions Conditional
Instruction Set Features
- Hardware Support for IEEE
  Single-Precision Instructions
- Hardware Support for IEEE
  Double-Precision Instructions
- Byte-Addressable (8-, 16-, 32-Bit Data)
- 32-Bit Address Range
- 8-Bit Overflow Protection
- Saturation
- Bit-Field Extract, Set, Clear
- Bit-Counting
- Normalization
1M-Bit On-Chip SRAM
- 512K-Bit Internal Program/Cache
  (16K 32-Bit Instructions)
- 512K-Bit Dual-Access Internal Data
  (64K Bytes)
32-Bit External Memory Interface (EMIF)
- Glueless Interface to Synchronous
  Memories: SDRAM and SBSRAM
- Glueless Interface to Asynchronous
  Memories: SRAM and EPROM
Four-Channel Bootloading
Direct-Memory-Access (DMA) Controller
With an Auxiliary Channel
16-Bit Host-Port Interface (HPI)
- Access to Entire Memory Map
Two Multichannel Buffered Serial Ports
(McBSPs)
- Direct Interface to T1/E1, MVIP, SCSA
  Framers
- ST-Bus-Switching Compatible
- Up to 256 Channels Each
- AC97-Compatible
- Serial-Peripheral-Interface (SPI)
  Compatible (Motorola™)
Two 32-Bit General-Purpose Timers
Flexible Phase-Locked-Loop (PLL) Clock
Generator
IEEE-1149.1 (JTAG)
Boundary-Scan-Compatible
429-Pin Ceramic Ball Grid Array (CBGA)
Package (GLP Suffix) and Land Grid Array
(CLGA) Package (ZMB Suffix)
0.18-µm/5-Level Metal Process
- CMOS Technology
3.3-V I/Os, 1.9-V Internal

IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
VelociTI is a trademark of Texas Instruments Incorporated.
Motorola is a trademark of Motorola, Inc.
TI is a trademark of Texas Instruments Incorporated.
Windows is a registered trademark of the Microsoft Corporation.

Highest Performance Floating-Point Digital
Signal Processor (DSP) SMJ320C6701
- 7-, 6-ns Instruction Cycle Time
- 140-, 167-MHz Clock Rate
- Eight 32-Bit Instructions/Cycle
- Up to 1 GFLOPS Performance
- Pin-Compatible With ’C6201 Fixed-Point DSP
SMJ: QML Processing to MIL-PRF-38535
SM: Standard Processing
Operating Temperature Ranges
- Extended (W) –55°C to 115°C
- Extended (S) –40°C to 90°C
VelociTI™ Advanced Very Long Instruction
Word (VLIW) ’C67x CPU Core
- Eight Highly Independent Functional Units:
  - Four ALUs (Floating- and Fixed-Point)
  - Two ALUs (Fixed-Point)
  - Two Multipliers (Floating- and
    Fixed-Point)
- Load-Store Architecture With 32 32-Bit
  General-Purpose Registers
- Instruction Packing Reduces Code Size
- All Instructions Conditional
Instruction Set Features
- Hardware Support for IEEE
  Single-Precision Instructions
- Hardware Support for IEEE
  Double-Precision Instructions
- Byte-Addressable (8-, 16-, 32-Bit Data)
- 32-Bit Address Range
- 8-Bit Overflow Protection
- Saturation
- Bit-Field Extract, Set, Clear
- Bit-Counting
- Normalization
1M-Bit On-Chip SRAM
- 512K-Bit Internal Program/Cache
  (16K 32-Bit Instructions)
- 512K-Bit Dual-Access Internal Data
  (64K Bytes)
32-Bit External Memory Interface (EMIF)
- Glueless Interface to Synchronous
  Memories: SDRAM and SBSRAM
- Glueless Interface to Asynchronous
  Memories: SRAM and EPROM
Four-Channel Bootloading
Direct-Memory-Access (DMA) Controller
With an Auxiliary Channel
16-Bit Host-Port Interface (HPI)
- Access to Entire Memory Map
Two Multichannel Buffered Serial Ports
(McBSPs)
- Direct Interface to T1/E1, MVIP, SCSA
  Framers
- ST-Bus-Switching Compatible
- Up to 256 Channels Each
- AC97-Compatible
- Serial-Peripheral-Interface (SPI)
  Compatible (Motorola™)
Two 32-Bit General-Purpose Timers
Flexible Phase-Locked-Loop (PLL) Clock
Generator
IEEE-1149.1 (JTAG)
Boundary-Scan-Compatible
429-Pin Ceramic Ball Grid Array (CBGA)
Package (GLP Suffix) and Land Grid Array
(CLGA) Package (ZMB Suffix)
0.18-µm/5-Level Metal Process
- CMOS Technology
3.3-V I/Os, 1.9-V Internal

IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
VelociTI is a trademark of Texas Instruments Incorporated.
Motorola is a trademark of Motorola, Inc.
TI is a trademark of Texas Instruments Incorporated.
Windows is a registered trademark of the Microsoft Corporation.

The SMJ320C67x DSPs are the floating-point DSP family in the SMJ320C6000 platform. The SMJ320C6701 (’C6701) device is based on the high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI™), making this DSP an excellent choice for multichannel and multifunction applications. With performance of up to 1 giga floating-point operations per second (GFLOPS) at a clock rate of 167 MHz, the ’C6701 offers cost-effective solutions to high-performance DSP programming challenges. The ’C6701 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide four floating-/fixed-point ALUs, two fixed-point ALUs, and two floating-/fixed-point multipliers. The ’C6701 can produce two multiply-accumulates (MACs) per cycle for a total of 334 million MACs per second (MMACS). The ’C6701 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals.

The ’C6701 includes a large bank of on-chip memory and has a powerful and diverse set of peripherals. Program memory consists of a 64K-byte block that is user-configurable as cache or memory-mapped program space. Data memory consists of two 32K-byte blocks of RAM. The peripheral set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM or SBSRAM and asynchronous peripherals.

The ’C6701 has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows. debugger interface for visibility into source code execution.

The SMJ320C67x DSPs are the floating-point DSP family in the SMJ320C6000 platform. The SMJ320C6701 (’C6701) device is based on the high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI™), making this DSP an excellent choice for multichannel and multifunction applications. With performance of up to 1 giga floating-point operations per second (GFLOPS) at a clock rate of 167 MHz, the ’C6701 offers cost-effective solutions to high-performance DSP programming challenges. The ’C6701 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide four floating-/fixed-point ALUs, two fixed-point ALUs, and two floating-/fixed-point multipliers. The ’C6701 can produce two multiply-accumulates (MACs) per cycle for a total of 334 million MACs per second (MMACS). The ’C6701 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals.

The ’C6701 includes a large bank of on-chip memory and has a powerful and diverse set of peripherals. Program memory consists of a 64K-byte block that is user-configurable as cache or memory-mapped program space. Data memory consists of two 32K-byte blocks of RAM. The peripheral set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM or SBSRAM and asynchronous peripherals.

The ’C6701 has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows. debugger interface for visibility into source code execution.

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Documentación técnica

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Documentación principal	Tipo	Título	Fecha
*	Data sheet	Floating-Point Digital Signal Processor datasheet (Rev. A)	27 jul 2009
*	SMD	SMJ320C6701 SMD 5962-98661	21 jun 2016
	Application note	Introduction to TMS320C6000 DSP Optimization	06 oct 2011
	More literature	QML Class V Product Portfolio	02 sep 2004
	More literature	SMJ320C6701/5962-9866101QXA (Rev. M)	03 may 2002
	More literature	Military C6000 DSPs (Rev. A)	08 may 2000

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Sonda de depuración

TMDSEMU560V2STM-U — Sonda de depuración USB de seguimiento del sistema XDS560v2

The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

No disponible en TI.com

Sonda de depuración

TMDSEMU560V2STM-UE — Sonda de depuración USB y ethernet de seguimiento del sistema XDS560v2

The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

No disponible en TI.com

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Lauterbach‘s TRACE32® tools are a suite of leading-edge hardware and software components that enables developers to analyze, optimize and certify all kinds of single- or multi-core Digital Signal processors (DSPs) which are a popular choice for audio and video processing as well as radar data (...)

Desde: Lauterbach GmbH

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