Detalles del producto

DSP type 1 C2x DSP (max) (MHz) 50 CPU 32-bit Rating Military Operating temperature range (°C) -55 to 125
DSP type 1 C2x DSP (max) (MHz) 50 CPU 32-bit Rating Military Operating temperature range (°C) -55 to 125
CPGA (GF) 305 2232.5625 mm² 47.25 x 47.25
  • Single-Chip Parallel Multiple Instruction/Multiple Data (MIMD) Digital Signal Processor (DSP)
  • More Than Two Billion RISC-Equivalent Operations per Second
  • Master Processor (MP)
    • 32-Bit Reduced Instruction Set Computing (RISC) Processor
    • IEEE-754 Floating-Point Capability
    • 4K-Byte Instruction Cache
    • 4K-Byte Data Cache
  • Four Parallel Processors (PP)
    • 32-Bit Advanced DSPs
    • 64-Bit Opcode Provides Many Parallel Operations per Cycle
    • 2K-Byte Instruction Cache and 8K-Byte Data RAM per PP
  • Transfer Controller (TC)
    • 64-Bit Data Transfers
    • Up to 400 Megabytes per Second (MBps) Transfer Rate
    • 32-Bit Addressing
    • Direct DRAM/VRAM Interface With Dynamic Bus Sizing
    • Intelligent Queuing and Cycle Prioritization
  • Video Controller (VC)
    • Provides Video Timing and Video Random-Access Memory (VRAM) Control
    • Dual-Frame Timers for Two Simultaneous Image-Capture and/or Display Systems
  • Big- or Little-Endian Operation
  • 50K-Byte On-Chip RAM
  • 4G-Byte Address Space
  • 20-ns Cycle Time
  • 3.3-V Operation
  • IEEE Standard 1149.1 Test Access Port (JTAG)
  • Operating Temperature Range
       –55°C to 125°C - M-Temperature
       –40°C to 85°C - A-Temperature

IEEE Standard 1149.1–1990, IEEE Standard Test Access Port and Boundary-Scan Architecture

  • Single-Chip Parallel Multiple Instruction/Multiple Data (MIMD) Digital Signal Processor (DSP)
  • More Than Two Billion RISC-Equivalent Operations per Second
  • Master Processor (MP)
    • 32-Bit Reduced Instruction Set Computing (RISC) Processor
    • IEEE-754 Floating-Point Capability
    • 4K-Byte Instruction Cache
    • 4K-Byte Data Cache
  • Four Parallel Processors (PP)
    • 32-Bit Advanced DSPs
    • 64-Bit Opcode Provides Many Parallel Operations per Cycle
    • 2K-Byte Instruction Cache and 8K-Byte Data RAM per PP
  • Transfer Controller (TC)
    • 64-Bit Data Transfers
    • Up to 400 Megabytes per Second (MBps) Transfer Rate
    • 32-Bit Addressing
    • Direct DRAM/VRAM Interface With Dynamic Bus Sizing
    • Intelligent Queuing and Cycle Prioritization
  • Video Controller (VC)
    • Provides Video Timing and Video Random-Access Memory (VRAM) Control
    • Dual-Frame Timers for Two Simultaneous Image-Capture and/or Display Systems
  • Big- or Little-Endian Operation
  • 50K-Byte On-Chip RAM
  • 4G-Byte Address Space
  • 20-ns Cycle Time
  • 3.3-V Operation
  • IEEE Standard 1149.1 Test Access Port (JTAG)
  • Operating Temperature Range
       –55°C to 125°C - M-Temperature
       –40°C to 85°C - A-Temperature

IEEE Standard 1149.1–1990, IEEE Standard Test Access Port and Boundary-Scan Architecture

The SMJ320C80 is a single-chip, MIMD parallel processor capable of performing over two billion operations per second. It consists of a 32-bit RISC master processor with a 100-MFLOPS (million floating-point operations per second) IEEE floating-point unit, four 32-bit parallel processing digital signal processors (DSPs), a transfer controller with up to 400-MBps off-chip transfer rate, and a video controller. All the processors are coupled tightly through an on-chip crossbar that provides shared access to on-chip RAM. This performance and programmability make the ’C80 ideally suited for video, imaging, and high-speed telecommunications applications.

The SMJ320C80 is a single-chip, MIMD parallel processor capable of performing over two billion operations per second. It consists of a 32-bit RISC master processor with a 100-MFLOPS (million floating-point operations per second) IEEE floating-point unit, four 32-bit parallel processing digital signal processors (DSPs), a transfer controller with up to 400-MBps off-chip transfer rate, and a video controller. All the processors are coupled tightly through an on-chip crossbar that provides shared access to on-chip RAM. This performance and programmability make the ’C80 ideally suited for video, imaging, and high-speed telecommunications applications.

Descargar Ver vídeo con transcripción Video

Documentación técnica

star =Principal documentación para este producto seleccionada por TI
No se encontraron resultados. Borre su búsqueda y vuelva a intentarlo.
Ver todo 3
Tipo Título Fecha
* Data sheet SMJ320C80 Digital Signal Processor datasheet (Rev. B) 30 jun 2002
* SMD SMJ320C80 SMD 5962-96791 21 jun 2016
More literature SM320C80/SMJ320C80 (Rev. C) 07 ago 2000

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Modelo de simulación

SM320C80 and SMJ320C80 BSDL Model

SGUM006.ZIP (7 KB) - BSDL Model
Encapsulado Pines Símbolos CAD, huellas y modelos 3D
CPGA (GF) 305 Ultra Librarian

Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

Los productos recomendados pueden tener parámetros, módulos de evaluación o diseños de referencia relacionados con este producto de TI.

Soporte y capacitación

Foros de TI E2E™ con asistencia técnica de los ingenieros de TI

El contenido lo proporcionan “tal como está” TI y los colaboradores de la comunidad y no constituye especificaciones de TI. Consulte los términos de uso.

Si tiene preguntas sobre la calidad, el paquete o el pedido de productos de TI, consulte el soporte de TI. ​​​​​​​​​​​​​​

Videos