Inicio Lógica y traducción de voltaje Biestables, latches y registros Biestables tipo D
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Biestables tipo D

SN54AS175B

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Hoja de datos

SN54AS175B

COMPRA POR ÚLTIMA VEZ
Hoja de datos Haga su pedido ahora

Detalles del producto

Number of channels 4 Technology family AS Input type Bipolar Output type Push-Pull Clock frequency (max) (MHz) 100 IOL (max) (mA) 20 IOH (max) (mA) -2 Supply current (max) (µA) 34000 Features Very high speed (tpd 5-10ns) Operating temperature range (°C) -55 to 125 Rating Military
Number of channels 4 Technology family AS Input type Bipolar Output type Push-Pull Clock frequency (max) (MHz) 100 IOL (max) (mA) 20 IOH (max) (mA) -2 Supply current (max) (µA) 34000 Features Very high speed (tpd 5-10ns) Operating temperature range (°C) -55 to 125 Rating Military
CDIP (J) 16 135.3552 mm² (— mm × — mm)
  • ’ALS174 and ’AS174 Contain Six Flip-Flops With Single-Rail Outputs
  • ’ALS175 and ’AS175B Contain Four Flip-Flops With Double-Rail Outputs
  • Buffered Clock and Direct-Clear Inputs
  • Applications Include:
    • Buffer/Storage Registers
    • Shift Registers
    • Pattern Generators
  • Fully Buffered Outputs for Maximum Isolation From External Disturbances (’AS Only)
  • ’ALS174 and ’AS174 Contain Six Flip-Flops With Single-Rail Outputs
  • ’ALS175 and ’AS175B Contain Four Flip-Flops With Double-Rail Outputs
  • Buffered Clock and Direct-Clear Inputs
  • Applications Include:
    • Buffer/Storage Registers
    • Shift Registers
    • Pattern Generators
  • Fully Buffered Outputs for Maximum Isolation From External Disturbances (’AS Only)

These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct-clear (CLR)\ input. The ’ALS175 and ’AS175B feature complementary outputs from each flip-flop.

Information at the data (D) inputs meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.

These circuits are fully compatible for use with most TTL circuits.

These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct-clear (CLR)\ input. The ’ALS175 and ’AS175B feature complementary outputs from each flip-flop.

Information at the data (D) inputs meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.

These circuits are fully compatible for use with most TTL circuits.
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Documentación técnica

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Documentación principal Tipo Título Opciones de formato Descargar la versión más reciente en inglés Fecha
* Hoja de datos Hex/Quadruple D-Type Flip-Flops With Clear datasheet (Rev. E) 23/05/2002
* SMD SN54AS175B SMD 5962-95537 21/06/2016

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