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Lógica y traducción de voltaje
Búferes, controladores y transceptores
Transceptores de uso general

SN74ABT2952A

ACTIVO

Transceptores y registros de bus octal con salidas de 3 estados

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SN74ABT2952A

ACTIVO
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Detalles del producto

Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Number of channels 8 IOL (max) (mA) 64 IOH (max) (mA) -32 Input type TTL Output type 3-State Features Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Technology family ABT Rating Catalog Operating temperature range (°C) -40 to 85
Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Number of channels 8 IOL (max) (mA) 64 IOH (max) (mA) -32 Input type TTL Output type 3-State Features Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Technology family ABT Rating Catalog Operating temperature range (°C) -40 to 85
SOIC (DW) 24 159.65 mm² 15.5 x 10.3
  • State-of-the-Art EPIC-II BTM BiCMOS Design Significantly Reduces Power Dissipation
  • Two 8-Bit Back-to-Back Registers Store Data Flowing in Both Directions
  • Noninverting Outputs
  • Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C
  • Latch-Up Performance Exceeds 500 mA Per JESD 17
  • ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
  • Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), Ceramic Flat (W) Package, and Plastic (NT) and Ceramic (JT) DIPs

EPIC is a trademark of Texas Instruments Incorporated.

  • State-of-the-Art EPIC-II BTM BiCMOS Design Significantly Reduces Power Dissipation
  • Two 8-Bit Back-to-Back Registers Store Data Flowing in Both Directions
  • Noninverting Outputs
  • Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C
  • Latch-Up Performance Exceeds 500 mA Per JESD 17
  • ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
  • Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), Ceramic Flat (W) Package, and Plastic (NT) and Ceramic (JT) DIPs

EPIC is a trademark of Texas Instruments Incorporated.

The 'ABT2952A transceivers consist of two 8-bit back-to-back registers that store data flowing in both directions between two bidirectional buses. Data on the A or B bus is stored in the registers on the low-to-high transition of the clock (CLKAB or CLKBA) input provided that the clock-enable (CLKENAB\ or CLKENBA\) input is low. Taking the output-enable (OEAB\ or OEBA\) input low accesses the data on either port.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54ABT2952A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT2952A is characterized for operation from -40°C to 85°C.

The 'ABT2952A transceivers consist of two 8-bit back-to-back registers that store data flowing in both directions between two bidirectional buses. Data on the A or B bus is stored in the registers on the low-to-high transition of the clock (CLKAB or CLKBA) input provided that the clock-enable (CLKENAB\ or CLKENBA\) input is low. Taking the output-enable (OEAB\ or OEBA\) input low accesses the data on either port.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54ABT2952A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT2952A is characterized for operation from -40°C to 85°C.
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Documentación técnica

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Tipo Título Fecha
* Data sheet Octal Bus Transceivers And Registers With 3-State Outputs datasheet (Rev. D) 01 ene 1998
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 jul 2021
Selection guide Logic Guide (Rev. AB) 12 jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 dic 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 ene 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 jun 2004
Application note Quad Flatpack No-Lead Logic Packages (Rev. D) 16 feb 2004
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 ago 2002
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 10 may 2002
Selection guide Advanced Bus Interface Logic Selection Guide 09 ene 2001
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 01 ago 1997
Application note Advanced BiCMOS Technology (ABT) Logic Characterization Information (Rev. B) 01 jun 1997
Application note Designing With Logic (Rev. C) 01 jun 1997
Application note Advanced BiCMOS Technology (ABT) Logic Enables Optimal System Design (Rev. A) 01 mar 1997
Application note Family of Curves Demonstrating Output Skews for Advanced BiCMOS Devices (Rev. A) 01 dic 1996
Application note Input and Output Characteristics of Digital Integrated Circuits 01 oct 1996
Application note Live Insertion 01 oct 1996
Application note Understanding Advanced Bus-Interface Products Design Guide 01 may 1996

Diseño y desarrollo

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Placa de evaluación

14-24-LOGIC-EVM — Módulo de evaluación genérico de productos lógicos para encapsulados D, DB, DGV, DW, DYY, NS y PW de

El módulo de evaluación 14-24-LOGIC-EVM (EVM) está diseñado para admitir cualquier dispositivo lógico que esté en un encapsulado D, DW, DB, NS, PW, DYY o DGV de 14 a 24 pines.

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