SN74ACT1073

ACTIVO

Redes de terminación de bus de 16 bits con función de retención de bus

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Hoja de datos

document-pdfAcrobat SN74ACT1073 datasheet (Rev. A) (Inglés)

SN74ACT1073

ACTIVO

Hoja de datos

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Detalles del producto

Technology family

ACT

Bits (#)

16

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Technology family

ACT

Bits (#)

16

Rating

Catalog

Operating temperature range (°C)

-40 to 85

SOP (NS)

20

98.28 mm² (12.6 mm × 7.8 mm)

SOIC (DW)

20

131.84 mm² (12.8 mm × 10.3 mm)

Designed to Ensure Defined Voltage Levels on Floating Bus Lines in CMOS Systems
4.5-V to 5.5-V V_CC Operation
Inputs Accept Voltages to 5.5 V
Reduces Undershoot and Overshoot Caused By Line Reflections
Repetitive Peak Forward Current ...I_FRM = 100 mA
Inputs Are TTL-Voltage Compatible
Low Power Consumption (Like CMOS)
Center-Pin V_CC and GND Configuration Minimizes High-Speed Switching Noise
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)

Designed to Ensure Defined Voltage Levels on Floating Bus Lines in CMOS Systems
4.5-V to 5.5-V V_CC Operation
Inputs Accept Voltages to 5.5 V
Reduces Undershoot and Overshoot Caused By Line Reflections
Repetitive Peak Forward Current ...I_FRM = 100 mA
Inputs Are TTL-Voltage Compatible
Low Power Consumption (Like CMOS)
Center-Pin V_CC and GND Configuration Minimizes High-Speed Switching Noise
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)

This device is designed to terminate bus lines in CMOS systems. The integrated low-impedance diodes clamp the voltage of undershoots and overshoots caused by line reflections and ensure signal integrity. The device also contains a bus-hold function that consists of a CMOS-buffer stage with a high-resistance feedback path between its output and its input. The SN74ACT1073 prevents bus lines from floating without using pullup or pulldown resistors.

The high-impedance inputs of these internal buffers are connected to the input terminals of the device. The feedback path on each internal buffer stage keeps a bus line tied to the bus holder at the last valid logic state generated by an active driver before the bus switches to the high-impedance state.

This device is designed to terminate bus lines in CMOS systems. The integrated low-impedance diodes clamp the voltage of undershoots and overshoots caused by line reflections and ensure signal integrity. The device also contains a bus-hold function that consists of a CMOS-buffer stage with a high-resistance feedback path between its output and its input. The SN74ACT1073 prevents bus lines from floating without using pullup or pulldown resistors.

The high-impedance inputs of these internal buffers are connected to the input terminals of the device. The feedback path on each internal buffer stage keeps a bus line tied to the bus holder at the last valid logic state generated by an active driver before the bus switches to the high-impedance state.

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Documentación principal	Tipo	Título	Opciones de formato	Descargar la versión más reciente en inglés	Fecha
*	Hoja de datos	SN74ACT1073 datasheet (Rev. A)			1/11/2002

SN74ACT1073

Redes de terminación de bus de 16 bits con función de retención de bus

SN74ACT1073

Detalles del producto

Documentación técnica

Pedidos y calidad

Soporte y capacitación

Foros de TI E2E™ con asistencia técnica de los ingenieros de TI