SN74ACT1284

Name: SN74ACT1284
Brand: TI
SKU: SN74ACT1284
Price: 0.597 USD

ACTIVO

Interfaces de bus de 7 bits con salidas de 3 estados

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Hoja de datos

document-pdfAcrobat SN54ACT1284, SN74ACT1284 datasheet (Rev. D) (Inglés)

SN74ACT1284

ACTIVO

Hoja de datos

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Detalles del producto

Bits (#)

7

Data rate (max) (Mbps)

12

Topology

Push-Pull

Vin (min) (V)

4.7

Vin (max) (V)

5.5

Applications

IEEE1284

Features

Output enable, Partial power down (Ioff), Single supply

Technology family

ACT

Supply current (max) (mA)

1.5

Rating

Catalog

Operating temperature range (°C)

0 to 70

Bits (#)

7

Data rate (max) (Mbps)

12

Topology

Push-Pull

Vin (min) (V)

4.7

Vin (max) (V)

5.5

Applications

IEEE1284

Features

Output enable, Partial power down (Ioff), Single supply

Technology family

ACT

Supply current (max) (mA)

1.5

Rating

Catalog

Operating temperature range (°C)

0 to 70

SOIC (DW)

20

131.84 mm² 12.8 x 10.3

SOP (NS)

20

98.28 mm² 12.6 x 7.8

SSOP (DB)

20

56.16 mm² 7.2 x 7.8

TSSOP (PW)

20

41.6 mm² 6.5 x 6.4

4.5-V to 5.5-V V_CC Operation
Inputs Accept Voltages to 5.5 V
Max t_pd of 20 ns at 5 V
3-State Outputs Directly Drive Bus Lines
Flow-Through Architecture Optimizes PCB Layout
Center-Pin V_CC and GND Configurations Minimize High-Speed Switching Noise
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
Designed for the IEEE 1284-I (Level-1 Type) and IEEE 1284-II (Level-2 Type) Electrical Specifications

4.5-V to 5.5-V V_CC Operation
Inputs Accept Voltages to 5.5 V
Max t_pd of 20 ns at 5 V
3-State Outputs Directly Drive Bus Lines
Flow-Through Architecture Optimizes PCB Layout
Center-Pin V_CC and GND Configurations Minimize High-Speed Switching Noise
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
Designed for the IEEE 1284-I (Level-1 Type) and IEEE 1284-II (Level-2 Type) Electrical Specifications

The ’ACT1284 devices are designed for asynchronous two-way communication between data buses. The control function minimizes external timing requirements.

The devices allow data transmission in either the A-to-B or the B-to-A direction for bits 1, 2, 3, and 4, depending on the logic level at the direction-control (DIR) input. Bits 5, 6, and 7, however, always transmit in the A-to-B direction.

The output drive for each mode is determined by the high-drive (HD) control pin. When HD is high, the high drive is delivered by the totem-pole configuration, and when HD is low, the outputs are open drain. This meets the drive requirements as specified in the IEEE 1284-I (level-1 type) and the IEEE 1284-II (level-2 type) parallel peripheral-interface specification.

The ’ACT1284 devices are designed for asynchronous two-way communication between data buses. The control function minimizes external timing requirements.

The devices allow data transmission in either the A-to-B or the B-to-A direction for bits 1, 2, 3, and 4, depending on the logic level at the direction-control (DIR) input. Bits 5, 6, and 7, however, always transmit in the A-to-B direction.

The output drive for each mode is determined by the high-drive (HD) control pin. When HD is high, the high drive is delivered by the totem-pole configuration, and when HD is low, the outputs are open drain. This meets the drive requirements as specified in the IEEE 1284-I (level-1 type) and the IEEE 1284-II (level-2 type) parallel peripheral-interface specification.

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