These devices contain two independent J-K\ positive-edge-triggered
flip-flops. A low level at the preset (
) or clear (
) inputs sets or resets the outputs
regardless of the levels of the other inputs. When and are inactive (high), data at the J
and K\ inputs meeting the setup-time requirements are transferred to
the outputs on the positive-going edge of the clock (CLK) pulse.
Clock triggering occurs at a voltage level and is not directly
related to the rise time of the clock pulse. Following the hold-time
interval, data at the J and K\ inputs can be changed without
affecting the levels at the outputs. These versatile flip-flops can
perform as toggle flip-flops by grounding K\ and tying J high. They
also can perform as D-type flip-flops if J and K\ are tied together.
The SN54ALS109A and SN54AS109A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS109A and SN74AS109A are characterized for operation from 0°C to 70°C.
| Tipo | Título | Fecha | ||
|---|---|---|---|---|
| * | Data sheet | Dual J-K Positive-Edge-Triggered Flip-Flops With Clear And Preset datasheet (Rev. B) | 01 ago 1995 | |
| Application note | Power-Up Behavior of Clocked Devices (Rev. B) | PDF | HTML | 15 dic 2022 | |
| Selection guide | Logic Guide (Rev. AB) | 12 jun 2017 | ||
| Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 02 dic 2015 | ||
| User guide | LOGIC Pocket Data Book (Rev. B) | 16 ene 2007 | ||
| Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 08 jul 2004 | ||
| Application note | TI IBIS File Creation, Validation, and Distribution Processes | 29 ago 2002 | ||
| Application note | Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) | 01 ago 1997 | ||
| Application note | Designing With Logic (Rev. C) | 01 jun 1997 | ||
| Application note | Input and Output Characteristics of Digital Integrated Circuits | 01 oct 1996 | ||
| Application note | Live Insertion | 01 oct 1996 | ||
| Application note | Advanced Schottky (ALS and AS) Logic Families | 01 ago 1995 |
Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.
El módulo de evaluación 14-24-LOGIC-EVM (EVM) está diseñado para admitir cualquier dispositivo lógico que esté en un encapsulado D, DW, DB, NS, PW, DYY o DGV de 14 a 24 pines.
| Paquete | Pasadores | Descargar |
|---|---|---|
| PDIP (N) | 16 | Ver opciones |
| SOIC (D) | 16 | Ver opciones |
| SOP (NS) | 16 | Ver opciones |
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