SN74ALS166

ACTIVO

Registros de desplazamiento en serie de carga paralela de 8 bits

Detalles del producto

Configuration Parallel-in, Serial-out Bits (#) 8 Technology family ALS Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type Bipolar Output type Push-Pull Clock frequency (MHz) 45 IOL (max) (mA) 8 IOH (max) (mA) -0.4 Supply current (max) (µA) 24000 Features High speed (tpd 10-50ns) Operating temperature range (°C) 0 to 70 Rating Catalog
Configuration Parallel-in, Serial-out Bits (#) 8 Technology family ALS Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type Bipolar Output type Push-Pull Clock frequency (MHz) 45 IOL (max) (mA) 8 IOH (max) (mA) -0.4 Supply current (max) (µA) 24000 Features High speed (tpd 10-50ns) Operating temperature range (°C) 0 to 70 Rating Catalog
PDIP (N) 16 181.42 mm² 19.3 x 9.4 SOIC (D) 16 59.4 mm² 9.9 x 6 SOP (NS) 16 79.56 mm² 10.2 x 7.8 SSOP (DB) 16 48.36 mm² 6.2 x 7.8
  • Synchronous Load
  • Direct Overriding Clear
  • Parallel-to-Serial Conversion
  • Package Options Include Plastic Small-Outline (D) and Shrink Small-Outline (DB) Packages and Standard Plastic (N) DIP
  • Synchronous Load
  • Direct Overriding Clear
  • Parallel-to-Serial Conversion
  • Package Options Include Plastic Small-Outline (D) and Shrink Small-Outline (DB) Packages and Standard Plastic (N) DIP

The SN74ALS166 parallel-load 8-bit shift register is compatible with most other TTL logic families. All inputs are buffered to lower the drive requirements. Input clamping diodes minimize switching transients and simplify system design.

These parallel-in or serial-in, serial-out registers have a complexity of 77 equivalent gates on the chip. They feature gated clocks (CLK and CLK INH) inputs and an overriding clear (CLR\) input. The parallel-in or serial-in modes are established by the shift/load (SH/LD\) input. When high, SH/LD\ enables the serial data (SER) input and couples the eight flip-flops for serial shifting with each clock pulse. When low, the parallel (broadside) data (A-H) inputs are enabled and synchronous loading occurs on the next clock pulse. During parallel loading, serial data flow is inhibited. Clocking is accomplished on the low-to-high-level edge of the clock pulse through a two-input positive-NOR gate, permitting one input to be used as a clock-enable or clock-inhibit function. Holding either of the clock inputs high inhibits clocking; holding either low enables the other clock input. This allows the system clock to be free running and the register can be stopped on command with the clock input. CLK INH should be changed to the high level only when CLK is high. The buffered CLR\ overrides all other inputs, including CLK, and sets all flip-flops to zero.

The SN74ALS166 is characterized for operation from 0°C to 70°C.

The SN74ALS166 parallel-load 8-bit shift register is compatible with most other TTL logic families. All inputs are buffered to lower the drive requirements. Input clamping diodes minimize switching transients and simplify system design.

These parallel-in or serial-in, serial-out registers have a complexity of 77 equivalent gates on the chip. They feature gated clocks (CLK and CLK INH) inputs and an overriding clear (CLR\) input. The parallel-in or serial-in modes are established by the shift/load (SH/LD\) input. When high, SH/LD\ enables the serial data (SER) input and couples the eight flip-flops for serial shifting with each clock pulse. When low, the parallel (broadside) data (A-H) inputs are enabled and synchronous loading occurs on the next clock pulse. During parallel loading, serial data flow is inhibited. Clocking is accomplished on the low-to-high-level edge of the clock pulse through a two-input positive-NOR gate, permitting one input to be used as a clock-enable or clock-inhibit function. Holding either of the clock inputs high inhibits clocking; holding either low enables the other clock input. This allows the system clock to be free running and the register can be stopped on command with the clock input. CLK INH should be changed to the high level only when CLK is high. The buffered CLR\ overrides all other inputs, including CLK, and sets all flip-flops to zero.

The SN74ALS166 is characterized for operation from 0°C to 70°C.

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Documentación técnica

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Tipo Título Fecha
* Data sheet Parallel-Load 8-Bit Shift Register datasheet (Rev. D) 25 ago 2000

Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

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