Inicio Lógica y traducción de voltaje Biestables, latches y registros Latches tipo D
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Biestables, latches y registros
Latches tipo D

SN74ALVCH16373

ACTIVO

Bloqueo transparente de tipo D de 16 bits con salidas de 3 estados

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SN74ALVCH16373

ACTIVO
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Detalles del producto

Number of channels 16 Technology family ALVC Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 3.6 Input type Standard CMOS Output type 3-State Clock frequency (max) (MHz) 150 IOL (max) (mA) 24 IOH (max) (mA) -24 Supply current (max) (µA) 40 Features Balanced outputs, Bus-hold, Flow-through pinout, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 85 Rating Catalog
Number of channels 16 Technology family ALVC Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 3.6 Input type Standard CMOS Output type 3-State Clock frequency (max) (MHz) 150 IOL (max) (mA) 24 IOH (max) (mA) -24 Supply current (max) (µA) 40 Features Balanced outputs, Bus-hold, Flow-through pinout, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 85 Rating Catalog
SSOP (DL) 48 164.358 mm² 15.88 x 10.35 TSSOP (DGG) 48 101.25 mm² 12.5 x 8.1
  • Member of the Texas Instruments Widebus™ Family
  • Operates From 1.65 V to 3.6 V
  • Max tpd of 3.6 ns at 3.3 V
  • ±24-mA Output Drive at 3.3 V
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)

Widebus is a trademark of Texas Instruments.
  • Member of the Texas Instruments Widebus™ Family
  • Operates From 1.65 V to 3.6 V
  • Max tpd of 3.6 ns at 3.3 V
  • ±24-mA Output Drive at 3.3 V
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)

Widebus is a trademark of Texas Instruments.

This 16-bit transparent D-type latch is designed for 1.65-V to 3.6-V VCC operation.

The SN74ALVCH16373 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. This device can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.

A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components. OE\ does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

This 16-bit transparent D-type latch is designed for 1.65-V to 3.6-V VCC operation.

The SN74ALVCH16373 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. This device can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.

A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components. OE\ does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
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Documentación técnica

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* Data sheet 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS--SN74ALVCH16373 datasheet (Rev. I) 26 ago 2005
Application note Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 15 dic 2022
Application note An Overview of Bus-Hold Circuit and the Applications (Rev. B) 17 sep 2018
Selection guide Logic Guide (Rev. AB) 12 jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 dic 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 ene 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 jul 2004
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 ago 2002
User guide ALVC Advanced Low-Voltage CMOS Including SSTL, HSTL, And ALB (Rev. B) 01 ago 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards 13 jun 2002
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 22 may 2002
Application note Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A) 08 sep 1999
Application note TI SN74ALVC16835 Component Specification Analysis for PC100 03 ago 1998
Application note Logic Solutions for PC-100 SDRAM Registered DIMMs (Rev. A) 13 may 1998
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 01 dic 1997
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 01 ago 1997
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 jun 1997
Application note Input and Output Characteristics of Digital Integrated Circuits 01 oct 1996
Application note Live Insertion 01 oct 1996
Application note Understanding Advanced Bus-Interface Products Design Guide 01 may 1996

Diseño y desarrollo

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Modelo de simulación

SN74ALVCH16373 IBIS Model (Rev. A)

SCEM194A.ZIP (63 KB) - IBIS Model
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SSOP (DL) 48 Ver opciones
TSSOP (DGG) 48 Ver opciones
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Pedidos y calidad

Información incluida:
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  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
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  • Lugar de fabricación
  • Lugar de ensamblaje

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