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SN74AS109A

ACTIVO

Biestables de tipo D con activación de borde positivo J-K doble con opciones de eliminación y preaju

Detalles del producto

Number of channels 2 Technology family AS Input type Bipolar Output type Push-Pull Clock frequency (MHz) 105 Supply current (max) (µA) 17000 IOL (max) (mA) 8 IOH (max) (mA) -0.4 Features Clear, High speed (tpd 10-50ns), Positive edge triggered, Preset Operating temperature range (°C) 0 to 70 Rating Catalog
Number of channels 2 Technology family AS Input type Bipolar Output type Push-Pull Clock frequency (MHz) 105 Supply current (max) (µA) 17000 IOL (max) (mA) 8 IOH (max) (mA) -0.4 Features Clear, High speed (tpd 10-50ns), Positive edge triggered, Preset Operating temperature range (°C) 0 to 70 Rating Catalog
SOIC (D) 16 59.4 mm² (9.9 mm × 6 mm) PDIP (N) 16 181.42 mm² (19.3 mm × 9.4 mm) SOP (NS) 16 79.56 mm² (10.2 mm × 7.8 mm)
  • Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs

 

 

  • Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs

 

 

These devices contain two independent J-K\ positive-edge-triggered flip-flops. A low level at the preset () or clear () inputs sets or resets the outputs regardless of the levels of the other inputs. When and are inactive (high), data at the J and K\ inputs meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K\ inputs can be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K\ and tying J high. They also can perform as D-type flip-flops if J and K\ are tied together.

The SN54ALS109A and SN54AS109A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS109A and SN74AS109A are characterized for operation from 0°C to 70°C.

 

These devices contain two independent J-K\ positive-edge-triggered flip-flops. A low level at the preset () or clear () inputs sets or resets the outputs regardless of the levels of the other inputs. When and are inactive (high), data at the J and K\ inputs meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K\ inputs can be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K\ and tying J high. They also can perform as D-type flip-flops if J and K\ are tied together.

The SN54ALS109A and SN54AS109A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS109A and SN74AS109A are characterized for operation from 0°C to 70°C.

 

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Documentación principal Tipo Título Opciones de formato Descargar la versión más reciente en inglés Fecha
* Hoja de datos Dual J-K Positive-Edge-Triggered Flip-Flops With Clear And Preset datasheet (Rev. B) 1/08/1995

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