SN74AUC126

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Búferes de alta velocidad, de 4 canales, 0.8 V a 2.7 V con salidas de 3 estados

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Hoja de datos

document-pdfAcrobat SN74AUC126 datasheet (Inglés)

SN74AUC126

ACTIVO

Hoja de datos

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Detalles del producto

Technology family

AUC

Number of channels

4

IOL (max) (mA)

9

Supply current (max) (µA)

10

IOH (max) (mA)

-9

Input type

Standard CMOS

Output type

3-State

Features

Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Technology family

AUC

Number of channels

4

IOL (max) (mA)

9

Supply current (max) (µA)

10

IOH (max) (mA)

-9

Input type

Standard CMOS

Output type

3-State

Features

Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 85

VQFN (RGY)

14

12.25 mm² (3.5 mm × 3.5 mm)

Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
I_off Supports Partial-Power-Down Mode Operation
Sub 1-V Operable
Max t_pd of 2.1 ns at 1.8 V
Low Power Consumption, 10-µA Max I_CC
±8-mA Output Drive at 1.8 V
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1500-V Charged-Device Model (C101)

Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
I_off Supports Partial-Power-Down Mode Operation
Sub 1-V Operable
Max t_pd of 2.1 ns at 1.8 V
Low Power Consumption, 10-µA Max I_CC
±8-mA Output Drive at 1.8 V
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1500-V Charged-Device Model (C101)

This quadruple bus buffer gate is designed for 0.8-V to 2.7-V V_CC operation, but is designed specifically for 1.6-V to 1.95-V V_CC operation.

The SN74AUC126 contains four independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low.

To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

This quadruple bus buffer gate is designed for 0.8-V to 2.7-V V_CC operation, but is designed specifically for 1.6-V to 1.95-V V_CC operation.

The SN74AUC126 contains four independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low.

To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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Documentación principal	Tipo	Título	Opciones de formato	Descargar la versión más reciente en inglés	Fecha
*	Hoja de datos	SN74AUC126 datasheet			1/12/2005

Diseño y desarrollo

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Placa de evaluación

14-24-NL-LOGIC-EVM — Módulo de evaluación genérico de productos lógicos para encapsulados sin plomo de 14 a 24 pines

El 14-24-NL-LOGIC-EVM es un módulo de evaluación flexible (EVM) diseñado para admitir cualquier dispositivo lógico o de traducción que tenga un encapsulado BQA, BQB, RGY, RSV, RJW o RHL de 14 a 24 pines.

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