SN74AVCAH164245

ACTIVO

Transceptor de bus de alimentación doble de 16 bits con traducción de tensión configurable

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Hoja de datos

document-pdfAcrobat SN74AVCAH164245 datasheet (Rev. A) (Inglés)

SN74AVCAH164245

ACTIVO

Hoja de datos

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Detalles del producto

Bits (#)

16

Data rate (max) (Mbps)

200

Topology

Push-Pull

Vin (min) (V)

1.4

Vin (max) (V)

3.6

Vout (min) (V)

1.4

Vout (max) (V)

3.6

Applications

GPIO

Features

Output damping resistors, Output enable, Overvoltage tolerant inputs, Partial power down (Ioff)

Technology family

AVC

Supply current (max) (mA)

0.08

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Bits (#)

16

Data rate (max) (Mbps)

200

Topology

Push-Pull

Vin (min) (V)

1.4

Vin (max) (V)

3.6

Vout (min) (V)

1.4

Vout (max) (V)

3.6

Applications

GPIO

Features

Output damping resistors, Output enable, Overvoltage tolerant inputs, Partial power down (Ioff)

Technology family

AVC

Supply current (max) (mA)

0.08

Rating

Catalog

Operating temperature range (°C)

-40 to 85

TVSOP (DGV)

48

62.08 mm² (9.7 mm × 6.4 mm)

TSSOP (DGG)

48

101.25 mm² (12.5 mm × 8.1 mm)

Member of the Texas Instruments Widebus™ Family
DOC™ Circuitry Dynamically Changes Output Impedance, Resulting in Noise Reduction Without Speed Degradation
Dynamic Drive Capability Is Equivalent to Standard Outputs With I_OH and I_OL of ±24 mA at 2.5-V V_CC
Control Inputs V_IH/V_IL Levels are Referenced to V_CCA Voltage
If Either V_CC Input Is at GND, Both Ports Are in the High-Impedance State
Overvoltage-Tolerant Inputs/Outputs Allow Mixed-Voltage-Mode Data Communications
I_off Supports Partial-Power-Down Mode Operation
Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.4-V to 3.6-V Power-Supply Range
Bus Hold on Data Inputs Eliminates the Need for External Pullup/ Pulldown Resistors
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

DOC and Widebus are trademarks of Texas Instruments.

Member of the Texas Instruments Widebus™ Family
DOC™ Circuitry Dynamically Changes Output Impedance, Resulting in Noise Reduction Without Speed Degradation
Dynamic Drive Capability Is Equivalent to Standard Outputs With I_OH and I_OL of ±24 mA at 2.5-V V_CC
Control Inputs V_IH/V_IL Levels are Referenced to V_CCA Voltage
If Either V_CC Input Is at GND, Both Ports Are in the High-Impedance State
Overvoltage-Tolerant Inputs/Outputs Allow Mixed-Voltage-Mode Data Communications
I_off Supports Partial-Power-Down Mode Operation
Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.4-V to 3.6-V Power-Supply Range
Bus Hold on Data Inputs Eliminates the Need for External Pullup/ Pulldown Resistors
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

DOC and Widebus are trademarks of Texas Instruments.

This 16-bit (dual-octal) noninverting bus transceiver uses two separate configurable power-supply rails. The A-port is designed to track V_CCA. V_CCA accepts any supply voltage from 1.4 V to 3.6 V. The B-port is designed to track V_CCB. V_CCB accepts any supply voltage from 1.4 V to 3.6 V. This allows for universal low-voltage bidirectional translation between any of the 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.

The SN74AVCAH164245 is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE)\ input can be used to disable the outputs so the buses are effectively isolated.

The SN74AVCAH164245 is designed so that the control pins (1DIR, 2DIR, 1OE\, and 2OE\) are supplied by V_CCA.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CCA through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. If either V_CC input is at GND, then both ports are in the high-impedance state.

This 16-bit (dual-octal) noninverting bus transceiver uses two separate configurable power-supply rails. The A-port is designed to track V_CCA. V_CCA accepts any supply voltage from 1.4 V to 3.6 V. The B-port is designed to track V_CCB. V_CCB accepts any supply voltage from 1.4 V to 3.6 V. This allows for universal low-voltage bidirectional translation between any of the 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.

The SN74AVCAH164245 is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE)\ input can be used to disable the outputs so the buses are effectively isolated.

The SN74AVCAH164245 is designed so that the control pins (1DIR, 2DIR, 1OE\, and 2OE\) are supplied by V_CCA.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CCA through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. If either V_CC input is at GND, then both ports are in the high-impedance state.

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Documentación principal	Tipo	Título	Opciones de formato	Fecha
*	Hoja de datos	SN74AVCAH164245 datasheet (Rev. A)		6/05/2004
	Nota sobre la aplicación	Schematic Checklist - A Guide to Designing With Fixed or Direction Control Translators	PDF \| HTML	2/10/2024
	Nota sobre la aplicación	Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators	PDF \| HTML	12/07/2024
	Nota sobre la aplicación	Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A)	PDF \| HTML	3/07/2024
	Guía de selección	Voltage Translation Buying Guide (Rev. A)		15/04/2021

Diseño y desarrollo

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