These octal bus transceivers are designed for asynchronous two-way communication between data buses. The control-function implementation allows for maximum flexibility in timing.
The ’HCT623 devices allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending upon the logic levels at the output-enable (OEAB and OEBA\) inputs.
The output-enable inputs disable the device so that the buses are effectively isolated. The dual-enable configuration gives the transceivers the capability to store data by simultaneously enabling OEAB and OEBA\. Each output reinforces its input in this transceiver configuration. When both OEAB and OEBA\ are enabled and all other data sources to the two sets of bus lines are in the high-impedance state, both sets of bus lines (16 total) remain at their last states. The 8-bit codes appearing on the two sets of buses are identical.
To ensure the high-impedance state during power up or power down, OEBA\ should be tied to VCC through a pullup resistor and OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver.
| Tipo | Título | Fecha | ||
|---|---|---|---|---|
| * | Data sheet | SN54HCT623, SN74HCT623 datasheet (Rev. C) | 18 mar 2003 | |
| Application note | Implications of Slow or Floating CMOS Inputs (Rev. E) | 26 jul 2021 | ||
| Selection guide | Logic Guide (Rev. AB) | 12 jun 2017 | ||
| Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 02 dic 2015 | ||
| User guide | LOGIC Pocket Data Book (Rev. B) | 16 ene 2007 | ||
| Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 08 jul 2004 | ||
| User guide | Signal Switch Data Book (Rev. A) | 14 nov 2003 | ||
| Application note | TI IBIS File Creation, Validation, and Distribution Processes | 29 ago 2002 | ||
| Application note | CMOS Power Consumption and CPD Calculation (Rev. B) | 01 jun 1997 | ||
| Application note | Designing With Logic (Rev. C) | 01 jun 1997 | ||
| Application note | SN54/74HCT CMOS Logic Family Applications and Restrictions | 01 may 1996 | ||
| Application note | Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc | 01 abr 1996 |
Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.
El módulo de evaluación 14-24-LOGIC-EVM (EVM) está diseñado para admitir cualquier dispositivo lógico que esté en un encapsulado D, DW, DB, NS, PW, DYY o DGV de 14 a 24 pines.
| Paquete | Pasadores | Descargar |
|---|---|---|
| PDIP (N) | 20 | Ver opciones |
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