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SN74LVC161284

ACTIVO

Interfaz de bus de 19 bits con salidas de 3 estados

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SN74LVC161284

ACTIVO
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Detalles del producto

Bits (#) 19 Data rate (max) (Mbps) 150 Topology Open drain Direction control (typ) Direction-controlled Vin (min) (V) 3 Vin (max) (V) 5.5 Vout (min) (V) 3 Vout (max) (V) 5.5 Applications IEEE1284 Features Output damping resistors, Output enable, Overvoltage tolerant inputs, Partial power down (Ioff) Prop delay (ns) 40 Technology family LVC Supply current (max) (mA) 45 Rating Catalog Operating temperature range (°C) 0 to 70
Bits (#) 19 Data rate (max) (Mbps) 150 Topology Open drain Direction control (typ) Direction-controlled Vin (min) (V) 3 Vin (max) (V) 5.5 Vout (min) (V) 3 Vout (max) (V) 5.5 Applications IEEE1284 Features Output damping resistors, Output enable, Overvoltage tolerant inputs, Partial power down (Ioff) Prop delay (ns) 40 Technology family LVC Supply current (max) (mA) 45 Rating Catalog Operating temperature range (°C) 0 to 70
SSOP (DL) 48 164.358 mm² (15.88 mm × 10.35 mm) TSSOP (DGG) 48 101.25 mm² (12.5 mm × 8.1 mm)
  • 1.4-k Pullup Resistors Integrated on All Open-Drain Outputs Eliminate the Need for Discrete Resistors
  • ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
  • Designed for the IEEE Std 1284-I (Level 1 Type) and IEEE Std 1284-II (Level 2 Type) Electrical Specifications
  • Flow-Through Architecture Optimizes PCB Layout
  • Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin-Shrink Small-Outline (DGG) Packages
  • 1.4-k Pullup Resistors Integrated on All Open-Drain Outputs Eliminate the Need for Discrete Resistors
  • ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
  • Designed for the IEEE Std 1284-I (Level 1 Type) and IEEE Std 1284-II (Level 2 Type) Electrical Specifications
  • Flow-Through Architecture Optimizes PCB Layout
  • Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin-Shrink Small-Outline (DGG) Packages

The SN74LVC161284 is designed for 3-V to 3.6-V VCC operation. This device provides asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements.

This device has eight bidirectional bits; data can flow in the A-to-B direction when DIR is high, and in the B-to-A direction when DIR is low. This device also has five drivers, which drive the cable side, and four receivers. The SN74LVC161284 has one receiver dedicated to the HOST LOGIC line and a driver to drive the PERI LOGIC line.

The output drive mode is determined by the high-drive (HD) control pin. When HD is high, the outputs are in a totem-pole configuration, and in an open-drain configuration when HD is low. This meets the drive requirements as specified in the IEEE Std 1284-I (level 1 type) and IEEE Std 1284-II (level 2 type) parallel peripheral-interface specifications. Except for HOST LOGIC IN and PERI LOGIC OUT, all cable-side pins have a 1.4-k integrated pullup resistor. The pullup resistor is switched off if the associated output driver is in the low state or if the output voltage is above VCC CABLE. If VCC CABLE is off, PERI LOGIC OUT is set to low.

The device has two supply voltages. VCC is designed for 3-V to 3.6-V operation. VCC CABLE supplies the inputs and output buffers of the cable side only and is designed for 3-V to 3.6-V and for 4.7-V to 5.5-V operation. Even when VCC CABLE is 3 V to 3.6 V, the cable-side I/O pins are 5-V tolerant.

The SN74LVC161284 is characterized for operation from 0°C to 70°C.

The SN74LVC161284 is designed for 3-V to 3.6-V VCC operation. This device provides asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements.

This device has eight bidirectional bits; data can flow in the A-to-B direction when DIR is high, and in the B-to-A direction when DIR is low. This device also has five drivers, which drive the cable side, and four receivers. The SN74LVC161284 has one receiver dedicated to the HOST LOGIC line and a driver to drive the PERI LOGIC line.

The output drive mode is determined by the high-drive (HD) control pin. When HD is high, the outputs are in a totem-pole configuration, and in an open-drain configuration when HD is low. This meets the drive requirements as specified in the IEEE Std 1284-I (level 1 type) and IEEE Std 1284-II (level 2 type) parallel peripheral-interface specifications. Except for HOST LOGIC IN and PERI LOGIC OUT, all cable-side pins have a 1.4-k integrated pullup resistor. The pullup resistor is switched off if the associated output driver is in the low state or if the output voltage is above VCC CABLE. If VCC CABLE is off, PERI LOGIC OUT is set to low.

The device has two supply voltages. VCC is designed for 3-V to 3.6-V operation. VCC CABLE supplies the inputs and output buffers of the cable side only and is designed for 3-V to 3.6-V and for 4.7-V to 5.5-V operation. Even when VCC CABLE is 3 V to 3.6 V, the cable-side I/O pins are 5-V tolerant.

The SN74LVC161284 is characterized for operation from 0°C to 70°C.
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Documentación técnica

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Documentación principal Tipo Título Opciones de formato Descargar la versión más reciente en inglés Fecha
* Hoja de datos SN74LVC161284 datasheet (Rev. J) 15/02/2005
Nota sobre la aplicación Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators PDF | HTML 12/07/2024
Nota sobre la aplicación Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) PDF | HTML 3/07/2024
Guía de selección Voltage Translation Buying Guide (Rev. A) 15/04/2021
Nota sobre la aplicación Logic Solutions For IEEE Std 1284 1/06/1999

Diseño y desarrollo

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Modelo de simulación

HSPICE Model for SN74LVC161284

SCEJ258.ZIP (102 KB) - Modelo HSpice
Productos y hardware compatibles
Modelo de simulación

SN74LVC161284 IBIS Model

SCAM032.ZIP (100 KB) - Modelo IBIS
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Encapsulado Pines Símbolos CAD, huellas y modelos 3D
SSOP (DL) 48 Ultra Librarian
TSSOP (DGG) 48 Ultra Librarian
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