SN74LVC1G80-Q1

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Biestable único de tipo D con activación de borde positivo de calidad automotriz

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Hoja de datos

document-pdfAcrobat SN74LVC1G80 -Q1 Single Positive-Edge-Triggered D-Type Flip-Flop datasheet (Rev. A) (Inglés) PDF | HTML

SN74LVC1G80-Q1

ACTIVO

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Detalles del producto

Number of channels

1

Technology family

LVC

Input type

Standard CMOS

Output type

Push-Pull

Clock frequency (max) (MHz)

150

IOL (max) (mA)

32

IOH (max) (mA)

-32

Supply current (max) (µA)

10

Features

Balanced outputs, Over-voltage tolerant inputs

Operating temperature range (°C)

-40 to 125

Rating

Automotive

Number of channels

1

Technology family

LVC

Input type

Standard CMOS

Output type

Push-Pull

Clock frequency (max) (MHz)

150

IOL (max) (mA)

32

IOH (max) (mA)

-32

Supply current (max) (µA)

10

Features

Balanced outputs, Over-voltage tolerant inputs

Operating temperature range (°C)

-40 to 125

Rating

Automotive

SOT-SC70 (DCK)

5

4.2 mm² (2 mm × 2.1 mm)

Qualified for automotive applications
AEC-Q100 qualified with the following results:
- ±4000V Human-Body Model (HBM) ESD classification level 3A
- ±1000V Charged-Device Model (CDM) ESD classification level C5
Supports 5V VCC operation
Inputs accept voltages to 5.5V
Supports down translation to VCC
Maximum tpd of 6ns at 3.3V
Low power consumption, 10µA maximum ICC
±24mA output drive at 3.3V
Ioff supports partial-power-down mode and back-drive protection

Qualified for automotive applications
AEC-Q100 qualified with the following results:
- ±4000V Human-Body Model (HBM) ESD classification level 3A
- ±1000V Charged-Device Model (CDM) ESD classification level C5
Supports 5V VCC operation
Inputs accept voltages to 5.5V
Supports down translation to VCC
Maximum tpd of 6ns at 3.3V
Low power consumption, 10µA maximum ICC
±24mA output drive at 3.3V
Ioff supports partial-power-down mode and back-drive protection

The SN74LVC1G80-Q1 device is an automotive AEC-Q100 qualified, single positive-edge-triggered D-type flip-flop that is designed for 1.65V to 5.5V VCC operation.

When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the level at the output.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device.

The SN74LVC1G80-Q1 device is an automotive AEC-Q100 qualified, single positive-edge-triggered D-type flip-flop that is designed for 1.65V to 5.5V VCC operation.

When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the level at the output.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device.

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Documentación principal	Tipo	Título	Opciones de formato	Descargar la versión más reciente en inglés	Fecha
*	Hoja de datos	SN74LVC1G80 -Q1 Single Positive-Edge-Triggered D-Type Flip-Flop datasheet (Rev. A)	PDF \| HTML		14/08/2026

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