SN74LVCZ245A

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Transceptor de bus octal con salidas de 3 estados

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Hoja de datos

document-pdfAcrobat SN74LVCZ245A datasheet (Rev. G) (Inglés)

SN74LVCZ245A

ACTIVO

Hoja de datos

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Detalles del producto

Number of channels

8

IOL (max) (mA)

24

IOH (max) (mA)

-24

Input type

TTL/CMOS

Output type

LVTTL

Features

Balanced outputs

Technology family

LVC

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Number of channels

8

IOL (max) (mA)

24

IOH (max) (mA)

-24

Input type

TTL/CMOS

Output type

LVTTL

Features

Balanced outputs

Technology family

LVC

Rating

Catalog

Operating temperature range (°C)

-40 to 85

SOP (NS)

20

98.28 mm² (12.6 mm × 7.8 mm)

TSSOP (PW)

20

41.6 mm² (6.5 mm × 6.4 mm)

SOIC (DW)

20

131.84 mm² (12.8 mm × 10.3 mm)

SSOP (DB)

20

56.16 mm² (7.2 mm × 7.8 mm)

Operate From 2.7 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max t_pd of 6.3 ns at 3.3 V
Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 3.3 V, T_A= 25°C
Typical V_OHV (Output V_OH Undershoot)
>2 V at V_CC = 3.3 V, T_A = 25°C
I_off and Power-Up 3-State Support Hot Insertion
Support Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V V_CC)
Latch-Up Performance Exceeds 100mA Per JESC 78, Class II

Operate From 2.7 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max t_pd of 6.3 ns at 3.3 V
Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 3.3 V, T_A= 25°C
Typical V_OHV (Output V_OH Undershoot)
>2 V at V_CC = 3.3 V, T_A = 25°C
I_off and Power-Up 3-State Support Hot Insertion
Support Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V V_CC)
Latch-Up Performance Exceeds 100mA Per JESC 78, Class II

This octal bus transceiver is designed for 2.7-V to 3.6-V V_CC operation.

The SN74LVCZ245A is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE)\ input can be used to disable the device so the buses are effectively isolated.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment.

When V_CC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for hot-insertion applications using I_off and power-up 3-state. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

This octal bus transceiver is designed for 2.7-V to 3.6-V V_CC operation.

The SN74LVCZ245A is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE)\ input can be used to disable the device so the buses are effectively isolated.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment.

When V_CC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for hot-insertion applications using I_off and power-up 3-state. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

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Documentación principal	Tipo	Título	Opciones de formato	Descargar la versión más reciente en inglés	Fecha
*	Hoja de datos	SN74LVCZ245A datasheet (Rev. G)			7/08/2003

Diseño y desarrollo

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Placa de evaluación

14-24-LOGIC-EVM — Módulo de evaluación genérico de productos lógicos para encapsulados D, DB, DGV, DW, DYY, NS y PW de

El módulo de evaluación (EVM) 14-24-LOGIC-EVM está diseñado para admitir cualquier dispositivo lógico que se encuentre en un encapsulado D, DW, DB, NS, PW, DYY o DGV de 14 a 24 pines.

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