SN74LVT240A

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Inversores de 8 canales, 2.7 V a 3.6 V con entradas CMOS compatibles con TTL y salidas de 3 estados

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Hoja de datos

document-pdfAcrobat SN74LVT240A datasheet (Rev. K) (Inglés)

SN74LVT240A

ACTIVO

Hoja de datos

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Detalles del producto

Technology family

LVT

Number of channels

8

IOL (max) (mA)

64

IOH (max) (mA)

-32

Supply current (max) (µA)

5000

Input type

TTL-Compatible CMOS

Output type

3-State

Features

Over-voltage tolerant inputs, Partial power down (Ioff), Power up 3-state, Ultra high speed (tpd <5ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Technology family

LVT

Number of channels

8

IOL (max) (mA)

64

IOH (max) (mA)

-32

Supply current (max) (µA)

5000

Input type

TTL-Compatible CMOS

Output type

3-State

Features

Over-voltage tolerant inputs, Partial power down (Ioff), Power up 3-state, Ultra high speed (tpd <5ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 85

SOIC (DW)

20

131.84 mm² (12.8 mm × 10.3 mm)

TSSOP (PW)

20

41.6 mm² (6.5 mm × 6.4 mm)

SSOP (DB)

20

56.16 mm² (7.2 mm × 7.8 mm)

SOP (NS)

20

98.28 mm² (12.6 mm × 7.8 mm)

Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V V_CC)
Supports Unregulated Battery Operation Down to 2.7 V
Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 3.3 V, T_A = 25°C
I_off and Power-Up 3-State Support Hot Insertion
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V V_CC)
Supports Unregulated Battery Operation Down to 2.7 V
Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 3.3 V, T_A = 25°C
I_off and Power-Up 3-State Support Hot Insertion
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

This octal buffer and line driver is designed specifically for low-voltage (3.3-V) V_CC operation, but with the capability to provide a TTL interface to a 5-V system environment.

The SN74LVT240A is organized as two 4-bit buffer/line drivers with separate output-enable (OE)\ inputs. When OE\ is low, the device passes data from the A inputs to the Y outputs. When OE\ is high, the outputs are in the high-impedance state.

When V_CC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for hot-insertion applications using I_off and power-up 3-state. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

This octal buffer and line driver is designed specifically for low-voltage (3.3-V) V_CC operation, but with the capability to provide a TTL interface to a 5-V system environment.

The SN74LVT240A is organized as two 4-bit buffer/line drivers with separate output-enable (OE)\ inputs. When OE\ is low, the device passes data from the A inputs to the Y outputs. When OE\ is high, the outputs are in the high-impedance state.

When V_CC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for hot-insertion applications using I_off and power-up 3-state. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

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Documentación principal	Tipo	Título	Opciones de formato	Descargar la versión más reciente en inglés	Fecha
*	Hoja de datos	SN74LVT240A datasheet (Rev. K)			14/01/2004

Diseño y desarrollo

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Placa de evaluación

14-24-LOGIC-EVM — Módulo de evaluación genérico de productos lógicos para encapsulados D, DB, DGV, DW, DYY, NS y PW de

El módulo de evaluación (EVM) 14-24-LOGIC-EVM está diseñado para admitir cualquier dispositivo lógico que se encuentre en un encapsulado D, DW, DB, NS, PW, DYY o DGV de 14 a 24 pines.

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