Inicio Lógica y traducción de voltaje Biestables, latches y registros Latches tipo D
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Lógica y traducción de voltaje
Biestables, latches y registros
Latches tipo D

SN74LVTH16373-EP

ACTIVO

Bloqueos transparentes de tipo D de 16 bits con salidas de 3 estados, 3.3 V ABT de producto mejorado

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SN74LVTH16373-EP

ACTIVO
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Detalles del producto

Number of channels 16 Technology family LVT Supply voltage (min) (V) 2.7 Supply voltage (max) (V) 3.6 Input type TTL-Compatible CMOS Output type 3-State Clock frequency (max) (MHz) 160 IOL (max) (mA) 64 IOH (max) (mA) -32 Supply current (max) (µA) 5000 Features Bus-hold, Flow-through pinout, Over-voltage tolerant inputs, Partial power down (Ioff), Power up 3-state, Ultra high speed (tpd <5ns) Operating temperature range (°C) -40 to 85 Rating HiRel Enhanced Product
Number of channels 16 Technology family LVT Supply voltage (min) (V) 2.7 Supply voltage (max) (V) 3.6 Input type TTL-Compatible CMOS Output type 3-State Clock frequency (max) (MHz) 160 IOL (max) (mA) 64 IOH (max) (mA) -32 Supply current (max) (µA) 5000 Features Bus-hold, Flow-through pinout, Over-voltage tolerant inputs, Partial power down (Ioff), Power up 3-state, Ultra high speed (tpd <5ns) Operating temperature range (°C) -40 to 85 Rating HiRel Enhanced Product
SSOP (DL) 48 164.358 mm² 15.88 x 10.35 TSSOP (DGG) 48 101.25 mm² 12.5 x 8.1
  • Controlled Baseline
    • One Assembly/Test Site, One Fabrication Site
  • Enhanced Diminishing Manufacturing Sources
    (DMS) Support
  • Enhanced Product-Change Notification
  • Qualification Pedigree(1)
  • Member of the Texas Instruments Widebus™ Family
  • State-of-the-Art Advanced BiCMOS Technology
    (ABT) Design for 3.3-V Operation and Low Static-
    Power Dissipation
  • Supports Mixed-Mode Signal Operation (5-V Input
    and Output Voltages With 3.3-V VCC)
  • Supports Unregulated Battery Operation Down to
    2.7 V
  • Typical VOLP (Output Ground Bounce) < 0.8 V
    at VCC = 3.3 V, TA = 25°C
  • Ioff and Power-Up Tri-State Support Hot Insertion
  • Bus Hold on Data Inputs Eliminates the Need for
    External Pullup/Pulldown Resistors
  • Distributed VCC and GND Pins Minimize High-
    Speed Switching Noise
  • Flow-Through Architecture Optimizes PCB Layout
  • Latch-Up Performance Exceeds 500 mA Per
    JESD 17
  • ESD Protection Exceeds JESD 22
    • 4000-V Human Body Model (A114-A)
    • 200-V Machine Model (A115-A)
  • Controlled Baseline
    • One Assembly/Test Site, One Fabrication Site
  • Enhanced Diminishing Manufacturing Sources
    (DMS) Support
  • Enhanced Product-Change Notification
  • Qualification Pedigree(1)
  • Member of the Texas Instruments Widebus™ Family
  • State-of-the-Art Advanced BiCMOS Technology
    (ABT) Design for 3.3-V Operation and Low Static-
    Power Dissipation
  • Supports Mixed-Mode Signal Operation (5-V Input
    and Output Voltages With 3.3-V VCC)
  • Supports Unregulated Battery Operation Down to
    2.7 V
  • Typical VOLP (Output Ground Bounce) < 0.8 V
    at VCC = 3.3 V, TA = 25°C
  • Ioff and Power-Up Tri-State Support Hot Insertion
  • Bus Hold on Data Inputs Eliminates the Need for
    External Pullup/Pulldown Resistors
  • Distributed VCC and GND Pins Minimize High-
    Speed Switching Noise
  • Flow-Through Architecture Optimizes PCB Layout
  • Latch-Up Performance Exceeds 500 mA Per
    JESD 17
  • ESD Protection Exceeds JESD 22
    • 4000-V Human Body Model (A114-A)
    • 200-V Machine Model (A115-A)

The SN74LVTH16373 is a 16-bit transparent D-type latch with tri-state outputs designed for low-voltage (3.3 V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.

This device is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. This device can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.

The SN74LVTH16373 is a 16-bit transparent D-type latch with tri-state outputs designed for low-voltage (3.3 V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.

This device is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. This device can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.
open-in-new Buscar otro/a Latches tipo D
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Documentación técnica

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Tipo Título Fecha
* Data sheet SN74LVTH16373-EP 3.3-V ABT 16-Bit Transparent D-Type Latch With Tri-State Outputs datasheet (Rev. B) PDF | HTML 29 jun 2016
* VID SN74LVTH16373-EP VID V6204712 21 jun 2016
Application note Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 15 dic 2022
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 jul 2021
Selection guide Logic Guide (Rev. AB) 12 jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 dic 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 ene 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 jul 2004
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 ago 2002
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 22 may 2002
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 10 may 2002
Selection guide Advanced Bus Interface Logic Selection Guide 09 ene 2001
Application note LVT-to-LVTH Conversion 08 dic 1998
Application note LVT Family Characteristics (Rev. A) 01 mar 1998
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 01 ago 1997
Application note Input and Output Characteristics of Digital Integrated Circuits 01 oct 1996
Application note Live Insertion 01 oct 1996
Application note Understanding Advanced Bus-Interface Products Design Guide 01 may 1996

Diseño y desarrollo

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Modelo de simulación

SN74LVTH16373 IBIS Model (Rev. C)

SCEM076C.ZIP (32 KB) - IBIS Model
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SSOP (DL) 48 Ver opciones
TSSOP (DGG) 48 Ver opciones
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Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

Soporte y capacitación

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