SN74LVTH273

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Biestables de tipo D octales ABT de 3.3 V con opción de eliminación

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Hoja de datos

document-pdfAcrobat SN54LVTH273, SN74LVTH273 datasheet (Rev. M) (Inglés)

SN74LVTH273

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Hoja de datos

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Detalles del producto

Number of channels

8

Technology family

LVT

Input type

TTL-Compatible CMOS

Output type

Push-Pull

Clock frequency (max) (MHz)

150

IOL (max) (mA)

64

IOH (max) (mA)

-32

Supply current (max) (µA)

5000

Features

Bus-hold, Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns)

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Number of channels

8

Technology family

LVT

Input type

TTL-Compatible CMOS

Output type

Push-Pull

Clock frequency (max) (MHz)

150

IOL (max) (mA)

64

IOH (max) (mA)

-32

Supply current (max) (µA)

5000

Features

Bus-hold, Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns)

Operating temperature range (°C)

-40 to 85

Rating

Catalog

TSSOP (PW)

20

41.6 mm² (6.5 mm × 6.4 mm)

SSOP (DB)

20

56.16 mm² (7.2 mm × 7.8 mm)

SOP (NS)

20

98.28 mm² (12.6 mm × 7.8 mm)

SOIC (DW)

20

131.84 mm² (12.8 mm × 10.3 mm)

Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V V_CC)
Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 3.3 V, T_A = 25°C
Support Unregulated Battery Operation Down to 2.7 V
Buffered Clock and Direct-Clear Inputs
Individual Data Input to Each Flip-Flop
I_off Supports Partial-Power-Down-Mode Operation
Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
Latch-Up Performance Exceeds 500 mA Per JESD 17
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)

Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V V_CC)
Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 3.3 V, T_A = 25°C
Support Unregulated Battery Operation Down to 2.7 V
Buffered Clock and Direct-Clear Inputs
Individual Data Input to Each Flip-Flop
I_off Supports Partial-Power-Down-Mode Operation
Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
Latch-Up Performance Exceeds 500 mA Per JESD 17
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)

These octal D-type flip-flops are designed specifically for low-voltage (3.3-V) V_CC operation, but with the capability to provide a TTL interface to a 5-V system environment.

The ’LVTH273 devices are positive-edge-triggered flip-flops with a direct-clear input. Information at the data (D) inputs meeting the setup-time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

These devices are fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.

These octal D-type flip-flops are designed specifically for low-voltage (3.3-V) V_CC operation, but with the capability to provide a TTL interface to a 5-V system environment.

The ’LVTH273 devices are positive-edge-triggered flip-flops with a direct-clear input. Information at the data (D) inputs meeting the setup-time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

These devices are fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.

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SN74HCT273

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Biestables tipo D octal con Clear Voltage range 4.5V to 5.5V, average propagation delay 22ns, average drive strength 4mA

Documentación técnica

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Ver todo 3

Documentación principal	Tipo	Título	Opciones de formato	Fecha
*	Hoja de datos	SN54LVTH273, SN74LVTH273 datasheet (Rev. M)		13/10/2003
	Nota sobre la aplicación	Power-Up Behavior of Clocked Devices (Rev. B)	PDF \| HTML	15/12/2022
	Nota sobre la aplicación	An Overview of Bus-Hold Circuit and the Applications (Rev. B)		17/09/2018

Diseño y desarrollo

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Placa de evaluación

14-24-LOGIC-EVM — Módulo de evaluación genérico de productos lógicos para encapsulados D, DB, DGV, DW, DYY, NS y PW de

El módulo de evaluación (EVM) 14-24-LOGIC-EVM está diseñado para admitir cualquier dispositivo lógico que se encuentre en un encapsulado D, DW, DB, NS, PW, DYY o DGV de 14 a 24 pines.

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