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Búferes y controladores inversores

SN74LVTH540

ACTIVO

Inversores de 8 canales, 2.7 V a 3.6 V, con retención de bus, entradas CMOS compatibles con TTL y sa

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SN74LVTH540

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Detalles del producto

Technology family LVT Number of channels 8 IOL (max) (mA) 64 IOH (max) (mA) -32 Supply current (max) (µA) 5000 Input type TTL-Compatible CMOS Output type 3-State Features Bus-hold, Over-voltage tolerant inputs, Partial power down (Ioff), Power up 3-state, Ultra high speed (tpd <5ns) Rating Catalog Operating temperature range (°C) -40 to 85
Technology family LVT Number of channels 8 IOL (max) (mA) 64 IOH (max) (mA) -32 Supply current (max) (µA) 5000 Input type TTL-Compatible CMOS Output type 3-State Features Bus-hold, Over-voltage tolerant inputs, Partial power down (Ioff), Power up 3-state, Ultra high speed (tpd <5ns) Rating Catalog Operating temperature range (°C) -40 to 85
SOIC (DW) 20 131.84 mm² (12.8 mm × 10.3 mm) TSSOP (PW) 20 41.6 mm² (6.5 mm × 6.4 mm) SSOP (DB) 20 56.16 mm² (7.2 mm × 7.8 mm)
  • Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)
  • Typical VOLP (Output Ground Bounce)
       <0.8 V at VCC = 3.3 V, TA = 25°C
  • Support Unregulated Battery Operation Down to 2.7 V
  • Ioff and Power-Up 3-State Support Hot Insertion
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Latch-Up Performance Exceeds 500 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
  • Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)
  • Typical VOLP (Output Ground Bounce)
       <0.8 V at VCC = 3.3 V, TA = 25°C
  • Support Unregulated Battery Operation Down to 2.7 V
  • Ioff and Power-Up 3-State Support Hot Insertion
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Latch-Up Performance Exceeds 500 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)

These octal buffers/drivers are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.

The ’LVTH540 devices are ideal for driving bus lines or buffer memory address registers. These devices feature inputs and outputs on opposite sides of the package that facilitate printed circuit board layout.

The 3-state control gate is a 2-input AND gate with active-low inputs so that if either output-enable (OE1\ or OE2\) input is high, all outputs are in the high-impedance state.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

These octal buffers/drivers are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.

The ’LVTH540 devices are ideal for driving bus lines or buffer memory address registers. These devices feature inputs and outputs on opposite sides of the package that facilitate printed circuit board layout.

The 3-state control gate is a 2-input AND gate with active-low inputs so that if either output-enable (OE1\ or OE2\) input is high, all outputs are in the high-impedance state.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.
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Documentación técnica

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Documentación principal Tipo Título Opciones de formato Descargar la versión más reciente en inglés Fecha
* Hoja de datos SN54LVTH540, SN74LVTH540 datasheet (Rev. G) 10/10/2003
Nota sobre la aplicación An Overview of Bus-Hold Circuit and the Applications (Rev. B) 17/09/2018

Diseño y desarrollo

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Placa de evaluación

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El módulo de evaluación (EVM) 14-24-LOGIC-EVM está diseñado para admitir cualquier dispositivo lógico que se encuentre en un encapsulado D, DW, DB, NS, PW, DYY o DGV de 14 a 24 pines.

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Modelo de simulación

SN74LVTH540 Behavioral SPICE Model

SCBM103.ZIP (7 KB) - Modelo PSpice
Productos y hardware compatibles
Modelo de simulación

SN74LVTH540 IBIS Model (Rev. A)

SCBM056 (116 KB) - Modelo IBIS
Productos y hardware compatibles
Encapsulado Pines Símbolos CAD, huellas y modelos 3D
SOIC (DW) 20 Ultra Librarian
TSSOP (PW) 20 Ultra Librarian
SSOP (DB) 20 Ultra Librarian
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