CY54FCT480T
- Function, Pinout, and Drive Compatible With FCT and F Logic
- Reduced VOH (Typically = 3.3 V) Versions of Equivalent FCT Functions
- Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics
- Ioff Supports Partial-Power-Down Mode Operation
- Matched Rise and Fall Times
- Fully Compatible With TTL Input and Output Logic Levels
- Two 8-Bit Parity Generators/Checkers
- Open-Drain Active-Low Parity-Error Output
- Expandable for Larger Word Widths
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
- CY54FCT480T
- 32-mA Output Sink Current
- 12-mA Output Source Current
- CY74FCT480T
- 64-mA Output Sink Current
- 32-mA Output Source Current
The \x92FCT480T devices are high-speed, dual, 8-bit parity generators/checkers. Each parity generator/checker accepts eight data bits and one parity bit as inputs, and generates a sum and parity-error (ERROR\) output. These devices can be used in odd-parity systems. ERROR\ is an open-drain output designed for easy expansion of the word width by a wired-OR connection of several \x92FCT480T devices. Because no additional logic is needed, the parity-generation or parity-checking times remain the same as for an individual \x92FCT480T device.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
기술 자료
| 상위 문서 | 유형 | 직함 | 형식 옵션 | 최신 영어 버전 다운로드 | 날짜 |
|---|---|---|---|---|---|
| * | 데이터 시트 | Dual 8-Bit Parity Generators/Checkers datasheet (Rev. B) | 2001. 10. 24 | ||
| * | 사용 설명서 | CYFCT Parameter Measurement Information | 2001. 4. 2 |
설계 및 개발
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| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| LCCC (FK) | 28 | Ultra Librarian |