데이터시트
SN74GTL2107
- Operates as a GTL-/GTL/GTL+ to LVTTL or LVTTL to GTL-/GTL/GTL+ Translator
- Series Termination on TTL Output of 30
- Latch-Up Testing Done to JEDEC Standard JESD 78
- ESD Performance Tested Per JESD 22
- 2000-V Human-Body Model
(A114-B, Class II) - 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
- 2000-V Human-Body Model
Xeon is a trademark of Intel Corporation.
The SN74GTL2107 is a 12-bit translator that interfaces between the 3.3-V LVTTL chip set I/O and the Xeon processor GTL-/GTL/GTL+ I/O. The device is designed for platform health management in dual-processor applications.
기술 문서
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모두 보기12 유형 | 직함 | 날짜 | ||
---|---|---|---|---|
* | Data sheet | SN74GTL2107 datasheet | 2006/07/01 | |
Application note | Implications of Slow or Floating CMOS Inputs (Rev. E) | 2021/07/26 | ||
Selection guide | Logic Guide (Rev. AB) | 2017/06/12 | ||
Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 2015/12/02 | ||
User guide | LOGIC Pocket Data Book (Rev. B) | 2007/01/16 | ||
Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 2004/07/08 | ||
Application note | TI IBIS File Creation, Validation, and Distribution Processes | 2002/08/29 | ||
Application note | Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices | 2002/05/10 | ||
User guide | GTLP/GTL Logic High-Performance Backplane Drivers Data Book (Rev. A) | 2001/09/15 | ||
Selection guide | Advanced Bus Interface Logic Selection Guide | 2001/01/09 | ||
Application note | GTL/BTL: A Low-Swing Solution for High-Speed Digital Logic (Rev. A) | 1997/03/01 | ||
Application note | Understanding Advanced Bus-Interface Products Design Guide | 1996/05/01 |
설계 및 개발
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패키지 | 핀 | 다운로드 |
---|---|---|
TSSOP (PW) | 28 | 옵션 보기 |
주문 및 품질
포함된 정보:
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
포함된 정보:
- 팹 위치
- 조립 위치