SN74VMEH22501A-EP
- Controlled Baseline
- One Assembly/Test Site, One Fabrication Site
- Enhanced Diminishing Manufacturing Sources (DMS) Support
- Enhanced Product-Change Notification
- Qualification Pedigree(1)
- Member of the Texas Instruments Widebus Family
- UBT Transceiver Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Modes
- OEC Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference (EMI)
- Compliant With VME64, 2eVME, and 2eSST Protocols Validated at TA = -40°C to 85°C
- Bus Transceiver Split LVTTL Port Provides a Feedback Path for Control and Diagnostics Monitoring
- I/O Interfaces are 5-V Tolerant
- B-Port Outputs (-48 mA/64 mA)
- Y and A-Port Outputs (-12 mA/12 mA)
- Ioff, Power-Up 3-State, and BIAS VCC Support Live Insertion
- Bus Hold on 3A-Port Data Inputs
- 26-Ω Equivalent Series Resistor on 3A Ports and Y Outputs
- Flow-Through Architecture Facilitates Printed Circuit Board Layout
- Distributed VCC and GND Pins Minimize High-Speed Switching Noise
- Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II - ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
The SN74VMEH22501A-EP 8-bit universal bus transceiver has two integral 1-bit three-wire bus transceivers and is designed for 3.3-V VCC operation with 5-V tolerant inputs. The UBT transceiver allows transparent, latched, and flip-flop modes of data transfer, and the separate LVTTL input and outputs on the bus transceivers provide a feedback path for control and diagnostics monitoring. This device provides a high-speed interface between cards operating at LVTTL logic levels and VME64, VME64x, or VME320(2) backplane topologies.
The SN74VMEH22501A-EP device is pin-for-pin compatible to the SN74VMEH22501 device (SCES357), but operates at a wider operating temperature range.
High-speed backplane operation is a direct result of the improved OEC circuitry and high drive that has been designed and tested into the VME64x backplane model. The B-port I/Os are optimized for driving large capacitive loads and include pseudo-ETL input thresholds (½ VCC ±50 mV) for increased noise immunity. These specifications support the 2eVME protocols in VME64x (ANSI/VITA 1.1) and 2eSST protocols in VITA 1.5.
With proper design of a 21-slot VME system, a designer can achieve 320-MB transfer rates on linear backplanes and, possibly, 1-GB transfer rates on the VME320 backplane.
All inputs and outputs are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs.
Active bus-hold circuitry holds unused or undriven 3A-port inputs at a valid logic state. Bus-hold circuitry is not provided on 1A or 2A inputs, any B-port input, or any control input. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
This device is fully specified for live-insertion applications using Ioff, power-up 3-state, and BIAS VCC. The Ioff circuitry prevents damaging current to backflow through the device when it is powered off/on. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The BIAS VCC circuitry precharges and preconditions the B-port input/output connections, preventing disturbance of active data on the backplane during card insertion or removal, and permits true live-insertion capability.
When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, output-enable (OE and OEBY) inputs should be tied to VCC through a pullup resistor and output-enable (OEAB) inputs should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the drive capability of the device connected to this input.
기술 문서
유형 | 직함 | 날짜 | ||
---|---|---|---|---|
* | Data sheet | SN74VMEH22501A-EP 8-Bit Universal Bus Transceiver and Two 1-Bit Bus Transceivers With Split LVTTL Port, Feedback Path, and 3-State Outputs datasheet (Rev. A) | PDF | HTML | 2015/11/09 |
* | VID | SN74VMEH22501A-EP VID V6205606 | 2016/06/21 | |
* | Radiation & reliability report | CVMEH22501AIDGVREP Reliability Report | 2012/06/04 | |
Selection guide | Logic Guide (Rev. AB) | 2017/06/12 | ||
Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 2015/12/02 | ||
User guide | LOGIC Pocket Data Book (Rev. B) | 2007/01/16 | ||
Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 2004/07/08 | ||
Application note | SN74VMEH22501 Universal Bus Transceiver for the VMEbus Backplane | 2003/05/14 | ||
More literature | SN74VMEH22501 Application Clip | 2003/03/04 | ||
Application note | VMEH22501 in 2eSST and Conventional VME Backplane Applications | 2002/10/07 | ||
Application note | Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices | 2002/05/10 |
설계 및 개발
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패키지 | 핀 | 다운로드 |
---|---|---|
TSSOP (DGG) | 48 | 옵션 보기 |
TVSOP (DGV) | 48 | 옵션 보기 |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치