Home Clocks & timing Clock generators
Home
Clocks & timing
Clock generators

LMK3H0102

ACTIVE

Bulk acoustic wave (BAW)-based PCIe Gen 1 to Gen 7-compliant referenceless clock generator

Order now
Data sheet

LMK3H0102

ACTIVE
Data sheet Order now

Product details

Number of outputs 2 Output type LP-HCSL, LVCMOS, LVDS Output frequency (max) (MHz) 400 Core supply voltage (V) 1.8, 2.5, 3.3 Output supply voltage (V) 1.8, 2.5, 3.3 Operating temperature range (°C) -40 to 85 Features Factory One-Time Programmable (OTP) memory, I2C, PCIe Gen 1 - 7 compliant, Pin programmable, Serial interface Rating Catalog
Number of outputs 2 Output type LP-HCSL, LVCMOS, LVDS Output frequency (max) (MHz) 400 Core supply voltage (V) 1.8, 2.5, 3.3 Output supply voltage (V) 1.8, 2.5, 3.3 Operating temperature range (°C) -40 to 85 Features Factory One-Time Programmable (OTP) memory, I2C, PCIe Gen 1 - 7 compliant, Pin programmable, Serial interface Rating Catalog
TQFN (RER) 16 9 mm² (3 mm × 3 mm)
  • Integrated BAW resonator, no need for external reference
  • Flexible frequency generation:
    • Two channel dividers: up to three unique output frequencies from 2.5MHz to 400MHz
    • LVCMOS outputs supported up to 200MHz: 1.8V, 2.5V, or 3.3V
    • Combination of AC-LVDS, DC-LVDS, LP-HCSL, and LVCMOS on OUT0 and OUT1 pins
    • Additional LVCMOS output for generation of up to 5 LVCMOS clocks
  • Total output frequency stability: ±25ppm
  • 2 functional modes: I2C or preprogrammed OTP
    • Fully configurable I2C address
  • PCIe Gen 1 to Gen 7 compliant: Common Clock with or without SSC, SRNS, and SRIS
  • Very low PCIe jitter with SSC:
    • PCIe Gen 3 Common Clock jitter: 135.3fs maximum (PCIe limit is 1ps)
    • PCIe Gen 4 Common Clock jitter: 135.3fs maximum (PCIe limit is 500fs)
    • PCIe Gen 5 Common Clock jitter: 57.5fs maximum (PCIe limit is 150fs)
    • PCIe Gen 6 Common Clock jitter: 34.5fs maximum (PCIe limit is 100fs)
    • PCIe Gen 7 Common Clock jitter: 29.6fs maximum (PCIe limit is 67fs)
  • Programmable SSC modulation depth
    • Preprogrammed: –0.1%, –0.25%, –0.3%, and –0.5% down spread at 200MHz FOD frequency
    • Register programmable: –0.1% to –3% down spread or ±0.05% to ±1.5% center spread
  • 1.8V to 3.3V supply voltage
  • Internal LDOs with –93.1dBc PSNR at 500kHz switching noise for LP-HCSL outputs
  • Start-up time: <1.5ms
  • Output-to-output skew: <50ps
  • Fail-safe digital input pins
  • Integrated BAW resonator, no need for external reference
  • Flexible frequency generation:
    • Two channel dividers: up to three unique output frequencies from 2.5MHz to 400MHz
    • LVCMOS outputs supported up to 200MHz: 1.8V, 2.5V, or 3.3V
    • Combination of AC-LVDS, DC-LVDS, LP-HCSL, and LVCMOS on OUT0 and OUT1 pins
    • Additional LVCMOS output for generation of up to 5 LVCMOS clocks
  • Total output frequency stability: ±25ppm
  • 2 functional modes: I2C or preprogrammed OTP
    • Fully configurable I2C address
  • PCIe Gen 1 to Gen 7 compliant: Common Clock with or without SSC, SRNS, and SRIS
  • Very low PCIe jitter with SSC:
    • PCIe Gen 3 Common Clock jitter: 135.3fs maximum (PCIe limit is 1ps)
    • PCIe Gen 4 Common Clock jitter: 135.3fs maximum (PCIe limit is 500fs)
    • PCIe Gen 5 Common Clock jitter: 57.5fs maximum (PCIe limit is 150fs)
    • PCIe Gen 6 Common Clock jitter: 34.5fs maximum (PCIe limit is 100fs)
    • PCIe Gen 7 Common Clock jitter: 29.6fs maximum (PCIe limit is 67fs)
  • Programmable SSC modulation depth
    • Preprogrammed: –0.1%, –0.25%, –0.3%, and –0.5% down spread at 200MHz FOD frequency
    • Register programmable: –0.1% to –3% down spread or ±0.05% to ±1.5% center spread
  • 1.8V to 3.3V supply voltage
  • Internal LDOs with –93.1dBc PSNR at 500kHz switching noise for LP-HCSL outputs
  • Start-up time: <1.5ms
  • Output-to-output skew: <50ps
  • Fail-safe digital input pins

The LMK3H0102 is a 2-output PCIe Gen 1 to Gen 7 compliant reference-less clock generator with Spread Spectrum Clocking (SSC) support. The part is based on TI proprietary Bulk Acoustic Wave (BAW) technology and provides ±25ppm clock outputs without any crystal or external clock reference. The device can provide two SSC clocks, two non-SSC clocks, or one SSC clock and one non-SSC clock at the same time. The device meets the full PCIe compliance from Gen 1 to Gen 7, including Common Clock with or without SSC, Separate Reference No Spread (SRNS), and Separate Reference Independent Spread (SRIS).

The device can be easily configured through either pins or I2C interface. An external DC/DC can be used to power the device. Refer to Power Supply Recommendations for detailed guidelines on power supply filtering and sourcing from DC/DC.

For OTP default settings for each LMK3H0102Axxx configuration, refer to the LMK3H0102 Configuration Guide.

The LMK3H0102 is a 2-output PCIe Gen 1 to Gen 7 compliant reference-less clock generator with Spread Spectrum Clocking (SSC) support. The part is based on TI proprietary Bulk Acoustic Wave (BAW) technology and provides ±25ppm clock outputs without any crystal or external clock reference. The device can provide two SSC clocks, two non-SSC clocks, or one SSC clock and one non-SSC clock at the same time. The device meets the full PCIe compliance from Gen 1 to Gen 7, including Common Clock with or without SSC, Separate Reference No Spread (SRNS), and Separate Reference Independent Spread (SRIS).

The device can be easily configured through either pins or I2C interface. An external DC/DC can be used to power the device. Refer to Power Supply Recommendations for detailed guidelines on power supply filtering and sourcing from DC/DC.

For OTP default settings for each LMK3H0102Axxx configuration, refer to the LMK3H0102 Configuration Guide.
filter Find other Clock generators
Download View video with transcript Video

Technical documentation

No results found. Please clear your search and try again.
View all 6
Top documentation Type Title Format options Date
* Data sheet LMK3H0102 Reference-Less 2-Differential or 5-Single-Ended Output PCIe Gen 1-7 Compliant Programmable BAW Clock Generator datasheet (Rev. E) PDF | HTML Oct 24, 2025
Application note EMI Reduction Strategies With Clocking Devices PDF | HTML Apr 21, 2025
User guide LMK3H0102 Configuration Guide PDF | HTML Nov 1, 2024
Application note Clocking for PCIe Applications PDF | HTML Nov 28, 2023
White paper The Importance of Clocks in Data Centers PDF | HTML Nov 21, 2023
Application note LMK3H0102 PCI Express Compliance Report PDF | HTML Nov 14, 2023

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

LMK3H0102EVM — LMK3H0102 evaluation module

The LMK3H0102 evaluation module provides a complete clocking platform to evaluate the clock performance, pin configuration, software configuration and features of the LMK3H0102 clock generator with integrated BAW (bulk acoustic wave)-based oscillator.
User guide: PDF | HTML
Supported products & hardware
In stock
Limit:
??asset.out-of-stock-ti_en_US??
Not available
GUI for evaluation module (EVM)

TICSPRO2-GUI — Programming sequence generation and EVM programming tool for clocking devices

Texas Instruments clocks and synthesizers (TICS) pro software is used to program the evaluation modules (EVMs) for product numbers with these prefixes: CDC, LMK and LMX. These products include phase-locked loops and voltage-controlled oscillators (PLL+VCO), synthesizers and clocking devices.

Supported products & hardware
Support software

TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices

Texas Instruments clocks and synthesizers (TICS) pro software is used to program the evaluation modules (EVMs) for product numbers with these prefixes: CDC, LMK and LMX. These products include phase-locked loops and voltage-controlled oscillators (PLL+VCO), synthesizers and clocking devices.

Supported products & hardware
Simulation model

LMK3H0102 IBIS Model

SNAM293.ZIP (138 KB) - IBIS model
Supported products & hardware
Design tool

PLLATINUMSIM-SW — PLL loop filter, phase noise, lock time, and spur simulation tool

PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.

Supported products & hardware
Package Pins CAD symbols, footprints & 3D models
TQFN (RER) 16 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

Ordering & quality

Recommended products may have parameters, evaluation modules or reference designs related to this TI product.

Support & training

TI E2E™ forums with technical support from TI engineers

View all forum topics

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos