首頁 數據轉換器 類比轉數位轉換器 (ADC) 精確 ADC
首頁
數據轉換器
類比轉數位轉換器 (ADC)
精確 ADC

ADC0820-N

現行

具追蹤/保持功能的 8 位元高速 µP 相容 A/D 轉換器

立即訂購
產品規格表

ADC0820-N

現行
產品規格表 立即訂購

產品詳細資料

Resolution (Bits) 8 Sample rate (max) (ksps) 658 Number of input channels 1 Interface type Parallel Architecture SAR Input type Single-ended Rating Catalog Reference mode External Input voltage range (max) (V) 8 Input voltage range (min) (V) 0 Operating temperature range (°C) -40 to 85 Power consumption (typ) (mW) 65 Analog supply voltage (min) (V) 4.5 Analog supply voltage (max) (V) 8 Digital supply (min) (V) 4.5 Digital supply (max) (V) 8
Resolution (Bits) 8 Sample rate (max) (ksps) 658 Number of input channels 1 Interface type Parallel Architecture SAR Input type Single-ended Rating Catalog Reference mode External Input voltage range (max) (V) 8 Input voltage range (min) (V) 0 Operating temperature range (°C) -40 to 85 Power consumption (typ) (mW) 65 Analog supply voltage (min) (V) 4.5 Analog supply voltage (max) (V) 8 Digital supply (min) (V) 4.5 Digital supply (max) (V) 8
SOIC (DW) 20 131.84 mm² (12.8 mm × 10.3 mm)
  • Built-In Track-and-Hold Function
  • No Missing Codes
  • No External Clocking
  • Single Supply—5 VDC
  • Easy Interface to All Microprocessors, or Operates Stand-Alone
  • Latched TRI-STATE Output
  • Logic Inputs and Outputs Meet Both MOS and T2L Voltage Level Specifications
  • Operates Ratiometrically or with any Reference Value Equal to or Less than VCC
  • 0V to 5V Analog Input Voltage Range with Single 5V Supply
  • No Zero or Full-Scale Adjust Required
  • Overflow Output Available for Cascading
  • 0.3 in. Standard Width 20-Pin PDIP
  • 20-Pin PLCC
  • 20-Pin SOIC

Key Specifications

  • Resolution: 8 Bits
  • Conversion Time
    • 2.5 µs Max (RD Mode)
    • 1.5 µs Max (WR-RD Mode)
  • Low Power: 75 mW Max
  • Total Unadjusted Error: ±½ LSB and ± 1 LSB

All trademarks are the property of their respective owners.

  • Built-In Track-and-Hold Function
  • No Missing Codes
  • No External Clocking
  • Single Supply—5 VDC
  • Easy Interface to All Microprocessors, or Operates Stand-Alone
  • Latched TRI-STATE Output
  • Logic Inputs and Outputs Meet Both MOS and T2L Voltage Level Specifications
  • Operates Ratiometrically or with any Reference Value Equal to or Less than VCC
  • 0V to 5V Analog Input Voltage Range with Single 5V Supply
  • No Zero or Full-Scale Adjust Required
  • Overflow Output Available for Cascading
  • 0.3 in. Standard Width 20-Pin PDIP
  • 20-Pin PLCC
  • 20-Pin SOIC

Key Specifications

  • Resolution: 8 Bits
  • Conversion Time
    • 2.5 µs Max (RD Mode)
    • 1.5 µs Max (WR-RD Mode)
  • Low Power: 75 mW Max
  • Total Unadjusted Error: ±½ LSB and ± 1 LSB

All trademarks are the property of their respective owners.

By using a half-flash conversion technique, the 8-bit ADC0820-N CMOS A/D offers a 1.5 µs conversion time and dissipates only 75 mW of power. The half-flash technique consists of 32 comparators, a most significant 4-bit ADC and a least significant 4-bit ADC.

The input to the ADC0820-N is tracked and held by the input sampling circuitry eliminating the need for an external sample-and-hold for signals moving at less than 100 mV/µs.

For ease of interface to microprocessors, the ADC0820-N has been designed to appear as a memory location or I/O port without the need for external interfacing logic.

By using a half-flash conversion technique, the 8-bit ADC0820-N CMOS A/D offers a 1.5 µs conversion time and dissipates only 75 mW of power. The half-flash technique consists of 32 comparators, a most significant 4-bit ADC and a least significant 4-bit ADC.

The input to the ADC0820-N is tracked and held by the input sampling circuitry eliminating the need for an external sample-and-hold for signals moving at less than 100 mV/µs.

For ease of interface to microprocessors, the ADC0820-N has been designed to appear as a memory location or I/O port without the need for external interfacing logic.
filter 尋找其它 精確 ADC
下載 觀看有字幕稿的影片 影片

技術文件

找不到結果。請清除您的搜尋條件，然後再試一次。
檢視所有 2
重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 ADC0820 8-Bit High Speed uP Compatible A/D Converter with Track/Hold Function datasheet (Rev. C) 2013/3/25
電子書 Best of Baker's Best: Precision Data Converters -- SAR ADCs 2015/5/21

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

設計工具

ADC-DAC-TO-VREF-SELECT-DESIGN-TOOL — The ADC-TO-VREF-SELECT tool enables the pairing of TI ADCs, DACs, and series voltage references.

The ADC-TO-VREF-SELECT tool enables the pairing of TI analog-to-digital converters (ADCs) and series voltage references. Users can select an ADC device and the desired reference voltage, and the tool will list up to two voltage reference recommendations.
支援產品和硬體
封裝 針腳 CAD 符號、佔位空間與 3D 模型
SOIC (DW) 20 Ultra Librarian
適用 TI 的評估品項標準條款與條件。

訂購與品質

建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。

支援與培訓

內含 TI 工程師技術支援的 TI E2E™ 論壇

以英文檢視所有論壇主題

內容係由 TI 和社群貢獻者依「現狀」提供，且不構成 TI 規範。檢視使用條款。

若有關於品質、封裝或訂購 TI 產品的問題，請參閱 TI 支援。​​​​​​​​​​​​​​

影片