ADC08DL502
- Single +1.9V ±0.1V Operation
- Duty Cycle Corrected Sample Clock
Key Specifications
- Resolution: 8 Bits
- Max Conversion Rate: 500 MSPS
- Code Error Rate: 10−18 (typ)
- ENOB @ 125 MHz Input: 7.5 Bits (typ)
- DNL: ±0.15 LSB (typ)
- Power
Consumption
- Operating in 1:2 Demux Output: 1.25W (typ)
- Power Down Mode: 3.3 mW (typ)
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The ADC08DL502 is a dual, low power, high performance, CMOS analog-to-digital converter. The ADC08DL502 digitizes signals to 8 bits of resolution at sample rates up to 500 MSPS. Consuming a typical 1.2 Watts in demultiplex mode at 500 MSPS from a single 1.9 Volt supply, this device is ensured to have no missing codes over the full operating temperature range. The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal sample-and-hold amplifier and the calibration schemes enable a very flat response of all dynamic parameters beyond Nyquist, producing a high 7.5 Effective Number of Bits (ENOB) with a 125 MHz input signal and a 500 MHz sample rate while providing a 10−18 Code Error Rate (C.E.R.)
The converter typically consumes 3.3 mW in the Power Down Mode and is available in a lead-free 144-lead LQFP and operates over the modified Industrial (-40°C ≤ TA ≤ +70°C) temperature range.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | Low Power, 8-Bit, Dual 500 MSPS A/D Converter datasheet (Rev. B) | 2013/3/15 |
設計與開發
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| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| LQFP (PGE) | 144 | Ultra Librarian |