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數據轉換器
類比轉數位轉換器 (ADC)
高速 ADC (≥10 MSPS)

ADC09QJ800

現行

具有 JESD204C 介面的四通道、9 位元、800-MSPS 類比轉數位轉換器 (ADC)

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產品規格表

ADC09QJ800

現行
產品規格表 立即訂購

產品詳細資料

Sample rate (max) (Msps) 800 Resolution (Bits) 9 Number of input channels 4 Interface type JESD204B, JESD204C Analog input BW (MHz) 6000 Features Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 1660 Architecture Folding Interpolating SNR (dB) 53.5 ENOB (bit) 8.5 SFDR (dB) 64 Operating temperature range (°C) -40 to 85 Input buffer Yes
Sample rate (max) (Msps) 800 Resolution (Bits) 9 Number of input channels 4 Interface type JESD204B, JESD204C Analog input BW (MHz) 6000 Features Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 1660 Architecture Folding Interpolating SNR (dB) 53.5 ENOB (bit) 8.5 SFDR (dB) 64 Operating temperature range (°C) -40 to 85 Input buffer Yes
FCCSP (AAV) 144 100 mm² 10 x 10
  • ADC Core:
    • Resolution: 9 Bit
    • Non-interleaved architecture
    • Internal dither reduces high-order harmonics
  • Performance specifications:
    • SNR (–1 dBFS, 97 MHz): 53.5 dBFS
    • ENOB (–1 dBFS, 97 MHz): 8.51 Bits
    • SFDR (–1 dBFS, 97 MHz): 64 dBFS
    • Noise floor (–20 dBFS, 97 MHz): –140.5 dBFS/Hz
  • Full-scale input voltage: 800 mVPP-DIFF
  • Full-power input bandwidth: 6 GHz
  • JESD204C Serial data interface:
    • Support for 2 to 8 (Quad/Dual channel) or 1 to 4 (Single channel) total SerDes lanes
    • Maximum baud-rate: 17.16 Gbps
    • 64B/66B and 8B/10B encoding modes
    • Subclass-1 support for deterministic latency
    • Compatible with JESD204B receivers
  • Optional internal sampling clock generation
    • Internal PLL and VCO (7.2–8.2 GHz)
  • SYSREF Windowing eases synchronization
  • Four clock outputs simplify system clocking
    • Reference clocks for FPGA or adjacent ADC
    • Reference clock for SerDes transceivers
  • Timestamp input and output for pulsed systems
  • Power consumption (800 MSPS):
    • Quad Channel: 420 mW / channel
    • Dual channel: 555 mW / channel
    • Single channel: 840 mW
  • Power supplies: 1.1 V, 1.9 V
  • ADC Core:
    • Resolution: 9 Bit
    • Non-interleaved architecture
    • Internal dither reduces high-order harmonics
  • Performance specifications:
    • SNR (–1 dBFS, 97 MHz): 53.5 dBFS
    • ENOB (–1 dBFS, 97 MHz): 8.51 Bits
    • SFDR (–1 dBFS, 97 MHz): 64 dBFS
    • Noise floor (–20 dBFS, 97 MHz): –140.5 dBFS/Hz
  • Full-scale input voltage: 800 mVPP-DIFF
  • Full-power input bandwidth: 6 GHz
  • JESD204C Serial data interface:
    • Support for 2 to 8 (Quad/Dual channel) or 1 to 4 (Single channel) total SerDes lanes
    • Maximum baud-rate: 17.16 Gbps
    • 64B/66B and 8B/10B encoding modes
    • Subclass-1 support for deterministic latency
    • Compatible with JESD204B receivers
  • Optional internal sampling clock generation
    • Internal PLL and VCO (7.2–8.2 GHz)
  • SYSREF Windowing eases synchronization
  • Four clock outputs simplify system clocking
    • Reference clocks for FPGA or adjacent ADC
    • Reference clock for SerDes transceivers
  • Timestamp input and output for pulsed systems
  • Power consumption (800 MSPS):
    • Quad Channel: 420 mW / channel
    • Dual channel: 555 mW / channel
    • Single channel: 840 mW
  • Power supplies: 1.1 V, 1.9 V

ADC09xJ800 is a family of quad, dual and single channel, 9-bit, 800 MSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 12-bit resolution makes the ADC09xJ800 ideally suited for a variety of multichannel communications and test systems.

Full-power input bandwidth (-3 dB) of 6 GHz enables direct RF sampling of of L-band and S-band.

ADC09xJ800 is a family of quad, dual and single channel, 9-bit, 800 MSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 12-bit resolution makes the ADC09xJ800 ideally suited for a variety of multichannel communications and test systems.

Full-power input bandwidth (-3 dB) of 6 GHz enables direct RF sampling of of L-band and S-band.
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* Data sheet ADC09xJ800 Quad, Dual, Single Channel, 800-MSPS, 9-bit, Analog-to-Digital Converter (ADC) with JESD204C Interface datasheet PDF | HTML 2021年 9月 28日

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開發板

ADC09QJ1300EVM — 具有 JESD204C 介面且適用於四通道、9 位元、1.3-GSPS ADC 的 ADC09QJ1300 評估模組

ADC09QJ1300 評估模組 (EVM) 可用於評估 ADC09QJ1300-Q1 裝置。ADC09QJ1300-Q1 是一款具有緩衝類比輸入的低功耗、9 位元、四通道、1.3-GSPS 類比轉數位轉換器 (ADC)，和具有 JESD204B/C 介面的整合式數位降壓轉換器。此 EVM 具有變壓器耦合類比輸入，可適應廣泛的訊號來源和頻率。

EVM 隨附 LMK04828 JESD204B/C 時鐘產生器，並且可配置為提供適用於完整 JESD204B/C 子類別 1 計時解決方案的超低抖動 ADC 裝置時鐘與 SYSREF。

ADC09QJ1300-Q1 和 LMK04828 (...)

使用指南: PDF
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開發板

TSW12QJ1600EVM — ADC12QJ1600-Q1 8 通道 (兩個同步 4 通道) 12 位元 1.6-GSPS JESD204C 介面 ADC 評估模組

TSW12QJ1600 評估模組 (EVM) 用於評估具備不同前端選項的 ADC12QJ1600-Q1 類比轉數位轉換器 (ADC)。ADC12QJ1600-Q1 是一款具有四個類比輸入通道的 12 位元 ADC，能以高達每秒 1.6 千兆取樣率 (GSPS) 運作。

此設計在相同印刷電路板 (PCB) 上有兩項 ADC12QJ1600-Q1 裝置，可用來展示多個 ADC 同步化、決定性延遲，並以各種前端選項 (AC 耦合變壓器；DC 耦合選項與 LMH32401) 測試 ADC 的性能。此設計也示範如何透過菊鏈將 PLL 參考輸出 (PLLREFO+、PLLREFO-) 從一個 ADC (...)

使用指南: PDF
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模擬型號

ADC12QJ1600 IBIS-AMI Model

SBAM512.ZIP (68 KB) - IBIS-AMI Model
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PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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