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數據轉換器
類比轉數位轉換器 (ADC)
高速 ADC (≥10 MSPS)

ADC10065

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10 位元 65-MSPS 類比轉數位轉換器 (ADC)

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ADC3910S065 現行 具有單一時脈週期延遲、高達 16 倍降取和數位比較器的 10 位元單通道 65MSPS ADC Lower power and smaller package size

ADC10065

現行
產品規格表 立即訂購

產品詳細資料

Sample rate (max) (Msps) 65 Resolution (Bits) 10 Number of input channels 1 Interface type Parallel CMOS, TTL Analog input BW (MHz) 400 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 68.4 Architecture Pipeline SNR (dB) 59.6 ENOB (Bits) 9.6 SFDR (dB) 80 Operating temperature range (°C) -40 to 85 Input buffer No
Sample rate (max) (Msps) 65 Resolution (Bits) 10 Number of input channels 1 Interface type Parallel CMOS, TTL Analog input BW (MHz) 400 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 68.4 Architecture Pipeline SNR (dB) 59.6 ENOB (Bits) 9.6 SFDR (dB) 80 Operating temperature range (°C) -40 to 85 Input buffer No
TSSOP (PW) 28 62.08 mm² (9.7 mm × 6.4 mm)
  • Single +3.0V Operation
  • Selectable 2 VP-P, 1.5 VP-P, or 1 VP-P Full-scale Input
  • 400 MHz −3 dB Input Bandwidth
  • Low Power Consumption
  • Standby Mode
  • On-Chip Reference and Sample-and-Hold Amplifier
  • Offset Binary or Two’s Complement Data Format
  • Separate Adjustable Output Driver Supply to Accommodate 2.5V and 3.3V Logic Families
  • 28-pin TSSOP Package

Key Specifications

  • Resolution 10 Bits
  • Conversion Rate 65 MSPS
  • Full Power Bandwidth 400 MHz
  • DNL ±0.3 LSB (typ)
  • SNR (fIN = 11 MHz) 59.6 dB (typ)
  • SFDR (fIN = 11 MHz) −80 dB (typ)
  • Power Consumption, 65 MHz 68.4 mW

All trademarks are the property of their respective owners.

  • Single +3.0V Operation
  • Selectable 2 VP-P, 1.5 VP-P, or 1 VP-P Full-scale Input
  • 400 MHz −3 dB Input Bandwidth
  • Low Power Consumption
  • Standby Mode
  • On-Chip Reference and Sample-and-Hold Amplifier
  • Offset Binary or Two’s Complement Data Format
  • Separate Adjustable Output Driver Supply to Accommodate 2.5V and 3.3V Logic Families
  • 28-pin TSSOP Package

Key Specifications

  • Resolution 10 Bits
  • Conversion Rate 65 MSPS
  • Full Power Bandwidth 400 MHz
  • DNL ±0.3 LSB (typ)
  • SNR (fIN = 11 MHz) 59.6 dB (typ)
  • SFDR (fIN = 11 MHz) −80 dB (typ)
  • Power Consumption, 65 MHz 68.4 mW

All trademarks are the property of their respective owners.

The ADC10065 is a monolithic CMOS analog-to-digital converter capable of converting analog input signals into 10-bit digital words at 65 Megasamples per second (MSPS). This converter uses a differential, pipeline architecture with digital error correction and an on-chip sample-and-hold circuit to provide a complete conversion solution, and to minimize power consumption, while providing excellent dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 400 MHz. Operating on a single 3.0V power supply, this device consumes just 68.4 mW at 65 MSPS, including the reference current. The Standby feature reduces power consumption to just 14.1 mW.

The differential inputs provide a full scale selectable input swing of 2.0 VP-P, 1.5 VP-P, 1.0 VP-P, with the possibility of a single-ended input. Full use of the differential input is recommended for optimum performance. An internal +1.2V precision bandgap reference is used to set the ADC full-scale range, and also allows the user to supply a buffered referenced voltage for those applications requiring increased accuracy. The output data format is user choice of offset binary or two’s complement.

This device is available in the 28-lead TSSOP package and will operate over the industrial temperature range of −40°C to +85°C.

The ADC10065 is a monolithic CMOS analog-to-digital converter capable of converting analog input signals into 10-bit digital words at 65 Megasamples per second (MSPS). This converter uses a differential, pipeline architecture with digital error correction and an on-chip sample-and-hold circuit to provide a complete conversion solution, and to minimize power consumption, while providing excellent dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 400 MHz. Operating on a single 3.0V power supply, this device consumes just 68.4 mW at 65 MSPS, including the reference current. The Standby feature reduces power consumption to just 14.1 mW.

The differential inputs provide a full scale selectable input swing of 2.0 VP-P, 1.5 VP-P, 1.0 VP-P, with the possibility of a single-ended input. Full use of the differential input is recommended for optimum performance. An internal +1.2V precision bandgap reference is used to set the ADC full-scale range, and also allows the user to supply a buffered referenced voltage for those applications requiring increased accuracy. The output data format is user choice of offset binary or two’s complement.

This device is available in the 28-lead TSSOP package and will operate over the industrial temperature range of −40°C to +85°C.
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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 ADC10065 10-Bit 65 MSPS 3V A/D Converter datasheet (Rev. H) 2013/4/18
使用指南 ADC10040/65/80 10-Bit, 40/65/80 MSPS, 3 Volt, 55.5/68.5/78.6 mW ADC User Guide 2012/2/20

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TSSOP (PW) 28 Ultra Librarian
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