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數據轉換器
類比轉數位轉換器 (ADC)
高速 ADC (≥10 MSPS)

ADC12D1800RF

現行

12 位元、雙 1.8GSPS 或單 3.6GSPS、射頻取樣類比轉數位轉換器 (ADC)

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產品規格表

ADC12D1800RF

現行
產品規格表 立即訂購

產品詳細資料

Sample rate (max) (Msps) 1800, 3600 Resolution (Bits) 12 Number of input channels 1, 2 Interface type Parallel LVDS Analog input BW (MHz) 2700 Features Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 4400 Architecture Folding Interpolating SNR (dB) 58.6 ENOB (Bits) 9.3 SFDR (dB) 71.7 Operating temperature range (°C) -40 to 85 Input buffer Yes
Sample rate (max) (Msps) 1800, 3600 Resolution (Bits) 12 Number of input channels 1, 2 Interface type Parallel LVDS Analog input BW (MHz) 2700 Features Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 4400 Architecture Folding Interpolating SNR (dB) 58.6 ENOB (Bits) 9.3 SFDR (dB) 71.7 Operating temperature range (°C) -40 to 85 Input buffer Yes
PBGA (NXA) 292 729 mm² (27 mm × 27 mm)
  • Excellent Noise and Linearity Up to and Above fIN = 2.7 GHz
  • Configurable to Either 3.6 GSPS Interleaved or 1800 MSPS Dual ADC
  • New DESCLKIQ Mode for High Bandwidth, High Sampling Rate Apps
  • Pin-Compatible with ADC1xD1x00, ADC12Dx00RF
  • AutoSync Feature for Multi-Chip Synchronization
  • Internally Terminated, Buffered, Differential Analog Inputs
  • Interleaved Timing Automatic and Manual Skew Adjust
  • Test Patterns at Output for System Debug
  • Time Stamp Feature to Capture External Trigger
  • Programmable Gain, Offset, and tAD Adjust
  • 1:1 Non-Demuxed or 1:2 Demuxed LVDS Outputs
  • Key Specifications
    • Resolution: 12 Bits
    • Interleaved 3.6 GSPS ADC (all typical)
      • IMD3 (Fin = 2.7GHz at -13dBFS) –62 dBc
      • IMD3 (Fin = 2.7GHz at -16dBFS) –64 dBc
      • Noise Floor Density -155.0 dBm/Hz
      • Power 4.29 W
    • Dual 1800 MSPS ADC, Fin = 498 MHz
      • ENOB 9.3 Bits (typ)
      • SNR 58.1 dB (typ)
      • SFDR 71.7 dBc (typ)
      • Power per Channel 2.15 W (typ)
  • Excellent Noise and Linearity Up to and Above fIN = 2.7 GHz
  • Configurable to Either 3.6 GSPS Interleaved or 1800 MSPS Dual ADC
  • New DESCLKIQ Mode for High Bandwidth, High Sampling Rate Apps
  • Pin-Compatible with ADC1xD1x00, ADC12Dx00RF
  • AutoSync Feature for Multi-Chip Synchronization
  • Internally Terminated, Buffered, Differential Analog Inputs
  • Interleaved Timing Automatic and Manual Skew Adjust
  • Test Patterns at Output for System Debug
  • Time Stamp Feature to Capture External Trigger
  • Programmable Gain, Offset, and tAD Adjust
  • 1:1 Non-Demuxed or 1:2 Demuxed LVDS Outputs
  • Key Specifications
    • Resolution: 12 Bits
    • Interleaved 3.6 GSPS ADC (all typical)
      • IMD3 (Fin = 2.7GHz at -13dBFS) –62 dBc
      • IMD3 (Fin = 2.7GHz at -16dBFS) –64 dBc
      • Noise Floor Density -155.0 dBm/Hz
      • Power 4.29 W
    • Dual 1800 MSPS ADC, Fin = 498 MHz
      • ENOB 9.3 Bits (typ)
      • SNR 58.1 dB (typ)
      • SFDR 71.7 dBc (typ)
      • Power per Channel 2.15 W (typ)

The 12-bit 1.8 GSPS ADC12D1800RF is an RF-sampling GSPS ADC that can directly sample input frequencies up to and above 2.7 GHz. The ADC12D1800RF augments the very large Nyquist zone of TI’s GSPS ADCs with excellent noise and linearity performance at RF frequencies, extending its usable range beyond the 3rd Nyquist zone.

The ADC12D1800RF provides a flexible LVDS interface which has multiple SPI programmable options to facilitate board design and FPGA/ASIC data capture. The LVDS outputs are compatible with IEEE 1596.3-1996 and supports programmable common mode voltage. The product is packaged in a lead-free 292-ball thermally enhanced BGA package over the rated industrial temperature range of –40°C to +85°C.

The 12-bit 1.8 GSPS ADC12D1800RF is an RF-sampling GSPS ADC that can directly sample input frequencies up to and above 2.7 GHz. The ADC12D1800RF augments the very large Nyquist zone of TI’s GSPS ADCs with excellent noise and linearity performance at RF frequencies, extending its usable range beyond the 3rd Nyquist zone.

The ADC12D1800RF provides a flexible LVDS interface which has multiple SPI programmable options to facilitate board design and FPGA/ASIC data capture. The LVDS outputs are compatible with IEEE 1596.3-1996 and supports programmable common mode voltage. The product is packaged in a lead-free 292-ball thermally enhanced BGA package over the rated industrial temperature range of –40°C to +85°C.
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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 ADC12D1800RF 12-Bit, Single 3.6 GSPS RF Sampling ADC datasheet (Rev. J) PDF | HTML 2014/11/11
應用說明 AN-2132 Synchronizing Multiple GSPS ADCs in a System: The AutoSync Feature (Rev. G) 2017/2/3
應用說明 Wide Bandwidth Receiver Implementation by Interleaving Two Giga-Sampling ADCs 2015/12/7
應用說明 Signal Chain Noise Figure Analysis 2014/10/29
應用說明 Synchronizing the Giga-Sample ADCs Interfaced with Multiple FPGAs 2014/8/6
應用說明 Maximizing SFDR Performance in the GSPS ADC: Spur Sources and Methods of Mitigat 2013/12/9
應用說明 AN-2128 ADC1xD1x00 Pin Compatibility (Rev. C) 2013/5/1
使用指南 Schematic and Layout Recommendations for the GSPS ADC 2013/4/29
應用說明 AN-2177 Using the LMH6554 as a ADC Driver (Rev. A) 2013/4/26
應用說明 From Sample Instant to Data Output: Understanding Latency in the GSPS ADC 2012/12/18
Product overview ADC12Dxx00RF Direct RF-Sampling ADC Family 2012/5/16
使用指南 12-Bit, Dual 1.6/1.8 GSPS or Single 3.2/3.6 GSPS A/D Converter Ref Bd User Guide 2012/1/25

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ADC-LD-BB — ADC 低失真平衡不平衡轉換器基板

配備 GSPS 類比轉數位轉換器 (ADC) 參考電路板的硬體套件中隨附一個 ADC-LD-BB 電路板。由於 ADC1xDxx00RB 的類比輸入為差動，且大多數訊號來源皆為單端，因此這些平衡不平衡轉換器板通常用於實現單端至差動轉換。若 I 和 Q 輸入同時以類似訊號驅動，可能需要額外的相同類型的平衡不平衡轉換器板。

順便一提，此平衡不平衡轉換器板也可用於進行差分至單端轉換。例如，在探索 GSPS ADC 參考電路板上的自動同步功能時，可能會在觀察單端範圍上的 DCLK± 或 RCOUT± 訊號時，使用此平衡不平衡轉換器基板。

ADC-LD-BB 使用 Anaren® 的 (...)

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WAVEVISION5 — WaveVision 5 Software

WaveVision 5 software is part of the WaveVision evaluation system that also includes WaveVision 5 Data Capture Board. The WaveVision 5 system is an easy-to-use data acquisition and analysis tool, designed to help users evaluate Texas Instruments' Signal Path solutions.

While WaveVision 5 software (...)

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模擬型號

ADC12D1000 IBIS Model

SNAM014.ZIP (41 KB) - IBIS 模型
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參考設計

TIDA-00071 — 每秒千兆次取樣 (GSPS) ADC 的電路圖和佈線圖建議

此參考設計是提供系統設計師在其系統中使用 GSPS ADC 之電路圖和佈線圖的指南。請將此參考設計與產品規格表一起使用 —— 產品規格表始終是最終權威。此外，ADC1xDxxxx(RF)RB 參考電路板也提供實用的參考設計。參考電路板的所有設計來源檔案以及 ADC 的 CAD/CAE 符號，都可在產品網頁或 TI-Designs 上下載。就本文件而言，ADC 或 GSPS ADC 係指 (...)

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參考設計

TIDA-00113 — 以單通道或雙通道模式驅動 GSPS ADC，適用於高頻寬應用

This design is intended to help the system designer in understanding tradeoffs and optimizing implementation for driving the Giga-Sample-Per-Second ADC with balun configurations for wideband applications.  The tradeoffs considered include balun construction, insertion loss, dynamic (...)

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參考設計

TIDA-00479 — 適用於 GSPS ADC 的最佳時鐘來源參考設計

ADC12D1600RFRB 參考設計提供了一個平台，用於展示包含時脈、電源管理和訊號處理的高速數位器應用。此參考設計採用 1.6 GSPS ADC12D1600RF 裝置、板載 FPGA Xilinx Virtex 4 和高效能時脈合成器 LMX2531，以滿足 9 位元 ENOB 高速數位器的系統需求。

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PBGA (NXA) 292 Ultra Librarian
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