產品詳細資料

Sample rate (max) (Msps) 1600 Resolution (Bits) 12 Number of input channels 4 Interface type JESD204B, JESD204C Analog input BW (MHz) 6000 Features Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 1910 Architecture Folding Interpolating SNR (dB) 57.4 ENOB (bit) 9 SFDR (dB) 64 Operating temperature range (°C) -40 to 85 Input buffer Yes
Sample rate (max) (Msps) 1600 Resolution (Bits) 12 Number of input channels 4 Interface type JESD204B, JESD204C Analog input BW (MHz) 6000 Features Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 1910 Architecture Folding Interpolating SNR (dB) 57.4 ENOB (bit) 9 SFDR (dB) 64 Operating temperature range (°C) -40 to 85 Input buffer Yes
FCCSP (AAV) 144 100 mm² 10 x 10
  • ADC Core:
    • Resolution: 12 Bit
    • Maximum sampling rate: 1.6 GSPS
    • Non-interleaved architecture
    • Internal dither reduces high-order harmonics
  • Performance specifications (–1 dBFS):
    • SNR (100 MHz): 57.4 dBFS
    • ENOB (100 MHz): 9.1 Bits
    • SFDR (100 MHz): 64 dBc
    • Noise floor (–20 dBFS): –147 dBFS
  • Full-scale input voltage: 800 mVPP-DIFF
  • Full-power input bandwidth: 6 GHz
  • JESD204C Serial data interface:
    • Support for 2 to 8 (Quad/Dual channel) or 1 to 4 (Single channel) total SerDes lanes
    • Maximum baud-rate: 17.16 Gbps
    • 64B/66B and 8B/10B encoding modes
    • Subclass-1 support for deterministic latency
    • Compatible with JESD204B receivers
  • Optional internal sampling clock generation
    • Internal PLL and VCO (7.2–8.2 GHz)
  • SYSREF Windowing eases synchronization
  • Four clock outputs simplify system clocking
    • Reference clocks for FPGA or adjacent ADC
    • Reference clock for SerDes transceivers
  • Timestamp input and output for pulsed systems
  • Power consumption (1 GSPS):
    • Quad Channel: 477 mW / channel
    • Dual channel: 700 mW / channel
    • Single channel: 1000 mW
  • Power supplies: 1.1 V, 1.9 V
  • ADC Core:
    • Resolution: 12 Bit
    • Maximum sampling rate: 1.6 GSPS
    • Non-interleaved architecture
    • Internal dither reduces high-order harmonics
  • Performance specifications (–1 dBFS):
    • SNR (100 MHz): 57.4 dBFS
    • ENOB (100 MHz): 9.1 Bits
    • SFDR (100 MHz): 64 dBc
    • Noise floor (–20 dBFS): –147 dBFS
  • Full-scale input voltage: 800 mVPP-DIFF
  • Full-power input bandwidth: 6 GHz
  • JESD204C Serial data interface:
    • Support for 2 to 8 (Quad/Dual channel) or 1 to 4 (Single channel) total SerDes lanes
    • Maximum baud-rate: 17.16 Gbps
    • 64B/66B and 8B/10B encoding modes
    • Subclass-1 support for deterministic latency
    • Compatible with JESD204B receivers
  • Optional internal sampling clock generation
    • Internal PLL and VCO (7.2–8.2 GHz)
  • SYSREF Windowing eases synchronization
  • Four clock outputs simplify system clocking
    • Reference clocks for FPGA or adjacent ADC
    • Reference clock for SerDes transceivers
  • Timestamp input and output for pulsed systems
  • Power consumption (1 GSPS):
    • Quad Channel: 477 mW / channel
    • Dual channel: 700 mW / channel
    • Single channel: 1000 mW
  • Power supplies: 1.1 V, 1.9 V

ADC12xJ1600 is a family of quad, dual and single channel, 12-bit, 1.6 GSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 12-bit resolution makes the ADC12xJ1600 ideally suited for a variety of multi-channel communications and test systems.

Full-power input bandwidth (-3 dB) of 6 GHz enables direct RF sampling of of L-band and S-band.

A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems.

JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB) routing. Interface modes support from 2 to 8 lanes (dual and quad channel devices) or 1 to 4 lanes (for the single channel device), with SerDes baud-rates up to 17.16 Gbps, to allow the optimal configuration for each application.

ADC12xJ1600 is a family of quad, dual and single channel, 12-bit, 1.6 GSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 12-bit resolution makes the ADC12xJ1600 ideally suited for a variety of multi-channel communications and test systems.

Full-power input bandwidth (-3 dB) of 6 GHz enables direct RF sampling of of L-band and S-band.

A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems.

JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB) routing. Interface modes support from 2 to 8 lanes (dual and quad channel devices) or 1 to 4 lanes (for the single channel device), with SerDes baud-rates up to 17.16 Gbps, to allow the optimal configuration for each application.

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* Data sheet ADC12xJ1600 Quad, Dual, or Single Channel 1.6-GSPS, 12-Bit, Analog-to-Digital Converter (ADC) with JESD204C Interface datasheet PDF | HTML 2021年 7月 16日
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開發板

ADC12QJ1600EVM — 具有 JESD204C 介面且適用於四通道、12 位元、1.6-GSPS ADC 的 ADC12QJ1600 評估模組

ADC12QJ1600 評估模組 (EVM) 可用於評估 ADC12QJ1600-Q1 產品。ADC12QJ1600-Q1 是一款具有緩衝類比輸入的低功耗、12 位元、四通道、1.6-GSPS 類比轉數位轉換器 (ADC),和具有 JESD204B/C 介面的整合式數位降壓轉換器。此 EVM 具有變壓器耦合類比輸入,可適應廣泛的訊號來源和頻率。

EVM 隨附 LMK04828 JESD204B/C 時鐘產生器,並且可配置為提供適用於完整 JESD204B/C 子類別 1 計時解決方案的超低抖動 ADC 裝置時鐘與 SYSREF。

ADC12QJ1600-Q1 和 LMK04828 (...)

使用指南: PDF
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TSW12QJ1600EVM — ADC12QJ1600-Q1 8 通道 (兩個同步 4 通道) 12 位元 1.6-GSPS JESD204C 介面 ADC 評估模組

TSW12QJ1600 評估模組 (EVM) 用於評估具備不同前端選項的 ADC12QJ1600-Q1 類比轉數位轉換器 (ADC)。ADC12QJ1600-Q1 是一款具有四個類比輸入通道的 12 位元 ADC,能以高達每秒 1.6 千兆取樣率 (GSPS) 運作。

此設計在相同印刷電路板 (PCB) 上有兩項 ADC12QJ1600-Q1 裝置,可用來展示多個 ADC 同步化、決定性延遲,並以各種前端選項 (AC 耦合變壓器;DC 耦合選項與 LMH32401) 測試 ADC 的性能。此設計也示範如何透過菊鏈將 PLL 參考輸出 (PLLREFO+、PLLREFO-) 從一個 ADC (...)

使用指南: PDF
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開發模組 (EVM) 的 GUI

SBAC269 ADC12QJ1600 Reference Design GUI

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產品
高速 ADC (≥10 MSPS)
ADC12QJ1600 具有 JESD204C 介面與整合式取樣時脈產生器的四通道 12 位元 1.6-GSPS ADC
模擬型號

ADC12QJ1600 IBIS-AMI Model

SBAM512.ZIP (68 KB) - IBIS-AMI Model
模擬工具

PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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FCCSP (AAV) 144 Ultra Librarian

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