ADC12QJ1600-SEP
- Radiation Tolerance:
- Total Ionizing Dose (TID): 30krad (Si)
- Single Event Latchup (SEL): 43 MeV-cm2/mg
- Single Event Upset (SEU) immune registers
- Space-enhanced plastic (space EP):
- Meets ASTM E595 outgassing specification
- Vendor item drawing (VID) V62/22610
- Temperature range: –55°C to 125°C
- One fabrication, assembly, and test site
- Wafer lot traceability
- Extended product life cycle
- Extended product change notification
- ADC Core:
- Resolution: 12 Bit
- Maximum sampling rate: 1.6GSPS
- Non-interleaved architecture
- Internal dither reduces high-order harmonics
- Performance specifications (–1dBFS):
- SNR (100 MHz): 57.4dBFS
- ENOB (100 MHz): 9.1 Bits
- SFDR (100 MHz): 64dBc
- Noise floor (–20 BFS): –147dBFS
- Full-scale input voltage: 800mVPP-DIFF
- Full-power input bandwidth: 6GHz
- JESD204C Serial data interface:
- Support for 2 to 8 total SerDes lanes
- Maximum baud-rate: 17.16Gbps
- 64B/66B and 8B/10B encoding modes
- Subclass-1 support for deterministic latency
- Compatible with JESD204B receivers
- Optional internal sampling clock generation
- Internal PLL and VCO (7.2 – 8.2GHz)
- SYSREF Windowing eases synchronization
- Four clock outputs simplify system clocking
- Reference clocks for FPGA or adjacent ADC
- Reference clock for SerDes transceivers
- Timestamp input and output for pulsed systems
- Power consumption (1GSPS): 1.9W
- Power supplies: 1.1V, 1.9V
ADC12QJ1600-SEP is a quad channel, 12-bit, 1.6GSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 12-bit resolution makes the device suited for a variety of mulch-chanel communications systems.
Full-power input bandwidth (-3 dB) of 6 GHz enables direct RF sampling of L-band and S-band.
A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems.
JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB) routing. Interface modes support from 2 to 8 lanes (dual and quad channel devices) or 1 to 4 lanes (for the single channel device), with SerDes baud-rates up to 17.16Gbps, to allow the optimal configuration for each application.
技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | ADC12QJ1600-SEP Quad Channel 1.6-GSPS, 12-Bit, Analog-to-Digital Converter (ADC) with JESD204C Interface datasheet (Rev. A) | PDF | HTML | 2025年 2月 24日 |
| * | Radiation & reliability report | ADC12QJ1600-SEP Production Flow and Reliability Report (Rev. A) | PDF | HTML | 2025年 3月 12日 |
設計與開發
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ADC12QJ1600EVM — 具有 JESD204C 介面且適用於四通道、12 位元、1.6GSPS ADC 的 ADC12QJ1600 評估模組
ADC09xJ800, ADC09xJ1300, ADC12xJ800 and ADC12xJ1600 IBIS-AMI Model (Rev. A)
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| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| FCCSP (ALR) | 144 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。