ADC32RF52
- 14-Bit, dual channel 1.5-GSPS ADC
- Noise spectral density:
- NSD = -153 dBFS/Hz (no AVG)
- NSD = -156 dBFS/Hz (2x AVG)
- NSD = -159 dBFS/Hz (4x AVG)
- Single core (non-interleaved) ADC architecture
- Aperture jitter: 50 fs
- Low close-in residual phase noise:
- -133 dBc/Hz at 10 kHz offset
- Spectral performance (f IN = 900 MHz, -4 dBFS):
- 2x internal averaging
- SNR: 66.8 dBFS
- SFDR HD2,3: 74 dBc
- SFDR worst spur: 90 dBFS
- Input fullscale: 1.0/1.1 Vpp (1/1.8 dBm)
- Code error rate (CER): 10 -15
- Full power input bandwidth (-3 dB): 1.6 GHz
- JESD204B serial data interface
- Maximum lane rate: 13 Gbps
- Supports subclass 1 deterministic latency
- Digital down-converters
- Up to four DDC per ADC channel
- Complex output: 4x, 16x to 128x decimation
- 48-bit NCO phase coherent frequency hopping
- Fast frequency hopping: < 1 us
- Power consumption: 1.8 W/channel (2x AVG)
- Power supplies: 1.8 V, 1.2 V
The ADC32RF52 is a single core 14-bit, 1.5 GSPS, dual channel analog to digital converter (ADC) that supports RF sampling with input frequencies up to 2 GHz. The design maximizes signal-to-noise ratio (SNR) and delivers a noise spectral density of -153 dBFS/Hz. Using additional internal ADCs along with on-chip signal averaging, the noise density improves to -156 dBFS/Hz (2x AVG) and -159 dBFS/Hz (4x AVG).
Each ADC channel can be connected to a quad-band digital down-converter (DDC) using a 48-bit NCO which supports phase coherent frequency hopping. Using the GPIO pins for NCO frequency control, frequency hopping can be achieved in less than 1 µs.
The ADC32RF52 supports the JESD204B serial data interface with subclass 1 deterministic latency using data rates up to 13 Gbps.
The power efficient ADC architecture consumes 1.4 W/ch at 1.5 Gsps and provides power scaling with lower sampling rates.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | ADC32RF52 Dual Channel 14-bit 1.5-GSPS RF Sampling Data Converter datasheet | PDF | HTML | 2023/9/27 | ||
| 類比設計期刊 | 高速轉換器奈奎斯特(Nyquist)孔周圍取樣 | PDF | HTML | Download English Version | PDF | HTML | 2025/5/23 | |
| 應用說明 | Comparing Active vs. Passive High-Speed/RF A/D Converter Front Ends | PDF | HTML | 2025/3/28 | |||
| 應用說明 | Evaluating High-Speed, RF ADC Converter Front-end Architectures | PDF | HTML | 2025/3/26 | |||
| 類比設計期刊 | 探索 RF 取樣資料轉換器在測試與測量應用中的快速跳頻 | PDF | HTML | Download English Version | PDF | HTML | 2024/9/23 | |
| 應用說明 | Improve SFDR Using Calibration in High-Speed ADCs | PDF | HTML | 2023/6/19 |
設計與開發
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ADC32RF55EVM — 適用於具有低 NSD 的雙通道 14 位元 3GSPS 射頻取樣 ADC 的 ADC32RF55 評估模組
ADC32RF55EVM-GUI — ADC3xRF5xEVM GUI installer/configuration generator
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| VQFNP (RTD) | 64 | Ultra Librarian |
訂購與品質
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。