ADC3443
- Quad Channel
- 14-Bit Resolution
- Single Supply: 1.8 V
- Serial LVDS Interface
- Flexible Input Clock Buffer With Divide-by-1, -2, -4
- SNR = 72.4 dBFS, SFDR = 87 dBc at
fIN = 70 MHz - Ultra-Low Power
Consumption:
- 98 mW/Ch at 125 MSPS
- Channel Isolation: 105 dB
- Internal Dither and Chopper
- Support for Multi-Chip Synchronization
- Pin-to-Pin Compatible With 12-Bit Version
- Package: VQFN-56 (8 mm × 8 mm)
The ADC344x devices are a high-linearity, ultra-low power, quad-channel, 14-bit, 25-MSPS to 125-MSPS, analog-to-digital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. An input clock divider allows more flexibility for system clock architecture design while the SYSREF input enables complete system synchronization.
The ADC344x family supports serial low-voltage differential signaling (LVDS) to reduce the number of interface lines, thus allowing for high system integration density. The serial LVDS interface is two-wire, where each ADC data are serialized and output over two LVDS pairs. Optionally, a one-wire serial LVDS interface is available. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock that is used to serialize the 14-bit output data from each channel. In addition to the serial data streams, the frame and bit clocks are transmitted as LVDS outputs.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | ADC344x Quad-Channel, 14-Bit, 25-MSPS to 125-MSPS, Analog-to-Digital Converters datasheet (Rev. B) | PDF | HTML | 2017/4/17 |
設計與開發
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ADC3443EVM — ADC3443 四通道、14 位元、80-MSPS 類比轉數位轉換器評估模組
ADC3443 EVM 展示了低功耗四路 80Msps 14 位元 ADC 的性能。 其中包括 ADC3443 裝置及 TI 電壓穩壓器，以提供必要的電壓。 ADC 的輸入預設連接至變壓器輸入，可連接至 50 ohm 單端訊號來源。 時鐘輸入可透過變壓器輸入提供，並可連接至 50 ohm 單端時鐘來源。 系統會提供 SYSREF 輸入，以允許完整的系統同步化。 透過板載 USB 連接和 GUI 提供暫存器存取權。
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| VQFN (RTQ) | 56 | Ultra Librarian |