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數據轉換器
類比轉數位轉換器 (ADC)
高速 ADC (≥10 MSPS)

ADC3648

現行

具有 LVDS 介面和高達 32768x 降取的 14 位元、雙通道、250MSPS ADC

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產品規格表

ADC3648

現行
產品規格表 立即訂購

產品詳細資料

Sample rate (max) (Msps) 250 Resolution (Bits) 14 Number of input channels 2 Interface type DDR LVDS Analog input BW (MHz) 1400 Features Decimating Filter, Differential Inputs, High Dynamic Range, High Performance, Input buffer, Low latency, Low power Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 470 Architecture Pipeline SNR (dB) 74 ENOB (Bits) 12 SFDR (dB) 83 Operating temperature range (°C) -40 to 85 Input buffer Yes
Sample rate (max) (Msps) 250 Resolution (Bits) 14 Number of input channels 2 Interface type DDR LVDS Analog input BW (MHz) 1400 Features Decimating Filter, Differential Inputs, High Dynamic Range, High Performance, Input buffer, Low latency, Low power Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 470 Architecture Pipeline SNR (dB) 74 ENOB (Bits) 12 SFDR (dB) 83 Operating temperature range (°C) -40 to 85 Input buffer Yes
VQFNP (RTD) 64 81 mm² (9 mm × 9 mm)
  • 14-bit, dual channel 250 and 500MSPS ADC
  • Noise spectral density: -158.5dBFS/Hz
  • Thermal Noise: 74.5dBFS
  • Single core (non-interleaved) ADC architecture
  • Power consumption:
    • 300mW/channel (500MSPS)
    • 250mW/channel (250MSPS)
  • Aperture jitter: 75fs
  • Buffered analog inputs
    • Programmable 100Ω to 200Ω termination
  • Input full scale: 2Vpp
  • Full power input bandwidth (-3dB): 1.4GHz
  • Spectral performance (fIN = 70MHz, -1dBFS):
    • SNR: 73.8dBFS
    • SFDR HD2,3: 84dBc
    • SFDR worst spur: 90dBFS
  • Digital down-converters (DDCs)
    • Up to four independent DDCs
    • Complex and real decimation
    • Decimation: /2, /4 to /32768 decimation
    • 48-bit NCO phase coherent frequency hopping
  • DDR, Serial LVDS interface
    • 14-bit Parallel DDR LVDS for DDC bypass
    • 16-bit Serial LVDS for decimation
    • 32-bit output option for high decimation
  • 14-bit, dual channel 250 and 500MSPS ADC
  • Noise spectral density: -158.5dBFS/Hz
  • Thermal Noise: 74.5dBFS
  • Single core (non-interleaved) ADC architecture
  • Power consumption:
    • 300mW/channel (500MSPS)
    • 250mW/channel (250MSPS)
  • Aperture jitter: 75fs
  • Buffered analog inputs
    • Programmable 100Ω to 200Ω termination
  • Input full scale: 2Vpp
  • Full power input bandwidth (-3dB): 1.4GHz
  • Spectral performance (fIN = 70MHz, -1dBFS):
    • SNR: 73.8dBFS
    • SFDR HD2,3: 84dBc
    • SFDR worst spur: 90dBFS
  • Digital down-converters (DDCs)
    • Up to four independent DDCs
    • Complex and real decimation
    • Decimation: /2, /4 to /32768 decimation
    • 48-bit NCO phase coherent frequency hopping
  • DDR, Serial LVDS interface
    • 14-bit Parallel DDR LVDS for DDC bypass
    • 16-bit Serial LVDS for decimation
    • 32-bit output option for high decimation

The ADC3648 and ADC3649 (ADC364x) are a 14-bit, 250MSPS and 500MSPS, dual channel analog to digital converter (ADC). The devices are designed for high signal-to-noise ratio (SNR) and deliver a noise spectral density of -158.5dBFS/Hz (500MSPS).

The power efficient ADC architecture consumes 300mW/ch at 500MSPS and provides power scaling with lower sampling rates (250mW/ch at 250MSPS).

The ADC364x includes an optional quad band digital down-converter (DDC) supporting wide band decimation by 2 to narrow band decimation by 32768. The DDC uses a 48-bit NCO which supports phase coherent and phase continuous frequency hopping.

The ADC364x is outfitted with a flexible LVDS interface. In decimation bypass mode, the device uses a 14-bit wide parallel DDR LVDS interface. When using decimation, the output data is transmitted using a serial LVDS interface reducing the number of lanes needed as decimation increases. For high decimation rates, the output resolution can be increased to 32-bit.

The ADC3648 and ADC3649 (ADC364x) are a 14-bit, 250MSPS and 500MSPS, dual channel analog to digital converter (ADC). The devices are designed for high signal-to-noise ratio (SNR) and deliver a noise spectral density of -158.5dBFS/Hz (500MSPS).

The power efficient ADC architecture consumes 300mW/ch at 500MSPS and provides power scaling with lower sampling rates (250mW/ch at 250MSPS).

The ADC364x includes an optional quad band digital down-converter (DDC) supporting wide band decimation by 2 to narrow band decimation by 32768. The DDC uses a 48-bit NCO which supports phase coherent and phase continuous frequency hopping.

The ADC364x is outfitted with a flexible LVDS interface. In decimation bypass mode, the device uses a 14-bit wide parallel DDR LVDS interface. When using decimation, the output data is transmitted using a serial LVDS interface reducing the number of lanes needed as decimation increases. For high decimation rates, the output resolution can be increased to 32-bit.
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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 ADC364x Dual-Channel, 14-Bit 250MSPS and 500MSPS Analog-to-Digital Converter (ADC) datasheet (Rev. B) PDF | HTML 2025/6/5
應用說明 Optimizing IFF Transponder Turnaround Time Using Ultra-Low Latency ADCs PDF | HTML 2026/7/16
類比設計期刊 高速轉換器奈奎斯特(Nyquist)孔周圍取樣 PDF | HTML Download English Version PDF | HTML 2025/5/23
應用說明 Comparing Active vs. Passive High-Speed/RF A/D Converter Front Ends PDF | HTML 2025/3/28
應用說明 Evaluating High-Speed, RF ADC Converter Front-end Architectures PDF | HTML 2025/3/26
應用說明 Improving MSPS ADC’s SFDR While Relaxing AAF Requirements and Using Integrated DDC Features PDF | HTML 2025/2/18

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開發板

ADC3669EVM — ADC3669 評估模組

ADC3669EVM 是可用於評估 ADC3669 系列高速 ADC 的評估模組 (EVM)。ADC3669EVM 配備一個 ADC3669。ADC3669 是一款具有 LVDS 介面的 16 位元雙通道 ADC，執行取樣率高達 500MSPS。ADC3669EVM 可評估所有裝置速度等級和通道數量。
使用指南: PDF | HTML
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計算工具

ADC3669-NOISE-ANALYSIS-CALC — Noise analysis calculation tool (SNR/SFDR) for ADC3669 with amplifier input.

Calculation tool for analyzing noise of ADC3669 with an amplifier as the input network.
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VQFNP (RTD) 64 Ultra Librarian
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