ADC3661
- 16-Bit 10-MSPS, 25-MSPS, or 65-MSPS ADCs
- Noise floor: –158 dBFS/Hz
- Low power consumption: 53 mW/ch (10 MSPS) to 94 mW/ch (65 MSPS)
- Latency: 1 cycle (1-wire SLVDS)
- Specified 16-bit, no missing codes
- INL: ± 3 LSB; DNL: ± 0.7 LSB
- Reference: external or internal
- Input bandwidth: 900 MHz (3 dB)
- Industrial temperature range: –40°C to +105°C
- On-chip digital filter (optional)
- Decimation by 2, 4, 8, 16, 32
- 32-bit NCO
- Serial LVDS digital interface (2-, 1- and 1/2-wire)
- Small footprint: 40-WQFN (5 mm × 5 mm) package
- Spectral performance (fIN = 10 MHz):
- SNR: 81.9 dBFS
- SFDR: 92-dBc HD2, HD3
- SFDR: 99-dBFS worst spur
The ADC3661, ADC3662, and ADC3663 (ADC366x) family of devices are low-noise, ultra-low power, 16-bit, 10-MSPS to 65-MSPS, high-speed, dual-channel, analog-to-digital converters (ADCs). Designed for low noise performance, these devices deliver a noise spectral density of –158 dBFS/Hz combined with great linearity and dynamic range. The ADC366x offers good dc precision together with IF sampling support making these devices suitable for a wide range of applications. High-speed control loops benefit from the short latency as low as only 1 clock cycle. The ADC consumes only 94 mW/ch at 65 MSPS and power consumption that scales well with lower sampling rates.
The ADC366x uses a serial LVDS (SLVDS) interface to output the data. The devices support a two-lane, a one-lane and a half-lane option. These devices are a pin-to-pin compatible family with 16-bit and 18-bit resolution and different speed grades. The devices come in a 40-pint QFN package (5 x 5 mm), and supports the extended industrial temperature range of –40°C to +105⁰C.
我們的 ADC3660 系列贏得 2021 年世界電子產品成就獎 (WEAA) 放大器/資料轉換類別的年度最佳產品。
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | ADC366x 16-Bit, 0.5-MSPS to 65-MSPS, Low-Noise, Low Power, Dual-Channel ADC datasheet (Rev. B) | PDF | HTML | 2022/9/27 | ||
| 應用說明 | Practical Clocking Considerations That Give Your Next High-Speed Converter Design an Edge (Rev. A) | PDF | HTML | 2025/4/11 | |||
| 類比設計期刊 | How to simplify AFE filtering via high‐speed ADCs with internal digital filters | 2020/1/10 |
設計與開發
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| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| WQFN (RSB) | 40 | Ultra Librarian |