ADC3908D025
- Sampling rate up to 125MSPS
- Latency: 1 clock cycle
- Low power (2 channel):
- 90mW at 125MSPS
- 56mW at 25MSPS
- 3mW in PD mode
- Small footprint: 32-VQFN (4mm x 4mm)
- Single or dual channel ADC
- Internal reference
- No missing codes, ±0.25 LSB INL
- Buffered, differential or single ended inputs
- Input bandwidth: 150MHz (3dB)
- Single 1.8V supply
- Optional 3.3VIO capability
- Industrial temperature range: -40°C to 105°C
- Parallel (SDR, DDR) CMOS interface
- Spectral performance (FSCLK = 125MSPS, fIN = 5 MHz):
- SNR: 49.8dBFS
- SFDR: 60dBFS
The ADC3908Dx and ADC3908Sx are a family of ultra-low power 8-bit 125MSPS high-speed dual and single channel analog-to-digital converters. High-speed control loops benefit from the short latency of only 1 clock cycle. The ADC consumes only 90mW at 125MSPS with a power consumption that scales with lower sampling rates.
The ADC3908Dx and ADC3908Sx uses parallel DDR or SDR CMOS interface to output the data, and can be driven at +1.8V or +3.3V to accommodate various receiver requirements. The analog input and output interface can be easily configured via pin control (Interface Configuration Table). The device is a pin-to-pin compatible family of ADCs with 8 and 10-bit resolution and different speed grades. The device is available in a 32-pin VQFN package, and supports industrial temperature range from -40 to +105°C.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | ADC3908Dx and ADC3908Sx 8-bit, 25 to 125MSPS Low Latency, Low Power, Small, Single and Dual Channel ADC with Integrated Input Buffers datasheet | PDF | HTML | 2023/5/11 | ||
| 應用說明 | High-Speed ADC: How to Properly Terminate Single-ended CMOS Digital Outputs | 2020/12/9 |
設計與開發
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ADC3910D125EVM — ADC3910D125 評估模組
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| VQFN (RSM) | 32 | Ultra Librarian |