ADS4128
- Maximum Sample Rate: 200 MSPS
- Ultralow Power with 1.8-V Single Supply:
- 230-mW Total Power at 200 MSPS
- High Dynamic Performance:
- SNR: 69 dBFS at 170 MHz
- SFDR: 85 dBc at 170 MHz
- Dynamic Power Scaling With Sample Rate
- Output Interface:
- Double Data Rate (DDR) LVDS with
Programmable Swing and Strength- Standard Swing: 350 mV
- Low Swing: 200 mV
- Default Strength: 100-Ω Termination
- 2× Strength: 50-Ω Termination
- 1.8-V Parallel CMOS Interface Also Supported
- Double Data Rate (DDR) LVDS with
- Programmable Gain up to 6 dB for SNR and
SFDR Trade-Off - DC Offset Correction
- Supports Low Input Clock Amplitude Down to 200
mVPP - Package: 7.00 mm × 7.00 mm VQFN-48
The ADS4128 is a 12-bit analog-to-digital converter (ADC) with sampling rates up to 200 MSPS. This device uses innovative design techniques to achieve high dynamic performance, while consuming extremely low power at 1.8-V supply. The device is well-suited for multi-carrier, wide-bandwidth communications applications.
The ADS4128 has fine-gain options that can be used to improve SFDR performance at lower full-scale input ranges, especially at high input frequencies. It includes a dc offset correction loop that can be used to cancel the ADC offset. At lower sampling rates, the ADC automatically operates at scaled-down power with no loss in performance.
The ADS4128 is available in a compact VQFN-48 package and is specified over the industrial temperature range (–40°C to 85°C).
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | ADS4128 12-Bit, 200-MSPS, Ultralow-Power ADC datasheet (Rev. A) | PDF | HTML | 2016/4/4 | ||
| * | 使用指南 | Interfacing Altera FPGAs to ADS4249 and DAC3482 (TIDA-00069 Reference Guide) | 2012/7/10 | |||
| 應用說明 | Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) | 2015/5/22 | ||||
| 應用說明 | Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) | 2013/7/19 |
設計與開發
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ANALOG-ENGINEER-CALC — PC software analog engineer's calculator
類比工程師的計算機旨在加速類比電路設計工程師定期使用的許多重複計算。此基於 PC 的工具提供圖形介面，列出各種常見計算，從使用回饋電阻器設定運算放大器增益到選擇適當的電路設計元件以穩定類比數位轉換器 (ADC) 驅動緩衝電路。
除了作為獨立工具使用外，此計算機還與類比工程師口袋參考中描述的概念相得益彰。
SBAC119 — TIGAR (Texas Instruments Graphical Evaluation of ADC Response Tool)
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| VQFN (RGZ) | 48 | Ultra Librarian |
訂購與品質
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。