ADS41B49
- ADS41B49: 14-Bit, 250 MSPS
ADS41B29: 12-Bit, 250 MSPS - Integrated High-Impedance
Analog Input Buffer:- Input Capacitance: 2 pF
- 200-MHz Input Resistance: 3 kΩ
- Maximum Sample Rate: 250 MSPS
- Ultralow Power:
- 1.8-V Analog Power: 180 mW
- 3.3-V Buffer Power: 96 mW
- I/O Power: 135 mW (DDR LVDS)
- High Dynamic Performance:
- SNR: 69 dBFS at 170 MHz
- SFDR: 82.5 dBc at 170 MHz
- Output Interface:
- Double Data Rate (DDR) LVDS with Programmable Swing and Strength:
- Standard Swing: 350 mV
- Low Swing: 200 mV
- Default Strength: 100-Ω Termination
- 2x Strength: 50-Ω Termination
- 1.8-V Parallel CMOS Interface Also Supported
- Double Data Rate (DDR) LVDS with Programmable Swing and Strength:
- Programmable Gain for SNR, SFDR Trade-Off
- DC Offset Correction
- Supports Low Input Clock Amplitude
- Package: VQFN-48 (7 mm × 7 mm)
The ADS41Bx9 are members of the ultralow-power ADS4xxx analog-to-digital converter (ADC) family, featuring integrated analog input buffers. These devices use innovative design techniques to achieve high dynamic performance, and consume extremely low power. The analog input pins have buffers, with benefits of constant performance and input impedance across a wide frequency range. The devices are well-suited for multi-carrier, wide bandwidth communications applications such as PA linearization.
The ADS41Bx9 have features such as digital gain and offset correction. The gain option can be used to improve SFDR performance at lower full-scale input ranges, especially at high input frequencies. The integrated dc offset correction loop can be used to estimate and cancel the ADC offset. At lower sampling rates, the ADC automatically operates at scaled-down power with no loss in performance.
The devices support both double data rate (DDR) low-voltage differential signaling (LVDS) and parallel CMOS digital output interfaces. The low data rate of the DDR LVDS interface (maximum 500 MBPS) makes using low-cost field-programmable gate array (FPGA)-based receivers possible. The devices have a low-swing LVDS mode that can be used to further reduce the power consumption. The strength of the LVDS output buffers can also be increased to support 50-Ω differential termination.
The devices are available in a compact VQFN-48 package and are specified over the industrial temperature range (–40°C to +85°C).
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | ADS41Bx9 14- and 12-Bit, 250-MSPS, Ultralow-Power ADCs with Analog Buffers datasheet (Rev. F) | PDF | HTML | 2016/2/11 | ||
| * | 使用指南 | Interfacing Altera FPGAs to ADS4249 and DAC3482 (TIDA-00069 Reference Guide) | 2012/7/10 | |||
| 應用說明 | Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) | 2015/5/22 | ||||
| 應用說明 | Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) | 2013/7/19 | ||||
| 應用說明 | Band-Pass Filter Design Techniques for High-Speed ADCs | 2012/2/27 | ||||
| 應用說明 | High-Speed, Analog-to-Digital Converter Basics | 2012/1/11 | ||||
| 應用說明 | Power Supply Design for the ADS41xx (Rev. A) | 2011/12/29 | ||||
| 應用說明 | CDCE62005 as Clock Solution for High-Speed ADCs | 2008/9/4 | ||||
| 應用說明 | CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters | 2008/6/8 | ||||
| 應用說明 | Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 | 2008/6/2 | ||||
| 應用說明 | QFN Layout Guidelines | 2006/7/28 |
設計與開發
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除了作為獨立工具使用外，此計算機還與類比工程師口袋參考中描述的概念相得益彰。
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SBAC119 — TIGAR (Texas Instruments Graphical Evaluation of ADC Response Tool)
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| VQFN (RGZ) | 48 | Ultra Librarian |
訂購與品質
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。