ADS4229
- Maximum Sample Rate: 250 MSPS
- Ultralow Power with Single 1.8-V Supply:
- 545-mW Total Power at 250 MSPS
- High Dynamic Performance:
- 80.8-dBc SFDR at 170 MHz
- 69.4-dBFS SNR at 170 MHz
- Crosstalk: > 90 dB at 185 MHz
- Programmable Gain Up to 6 dB for
SNR and SFDR Trade-off - DC Offset Correction
- Output Interface Options:
- 1.8-V Parallel CMOS Interface
- DDR LVDS With Programmable Swing:
- Standard Swing: 350 mV
- Low Swing: 200 mV
- Supports Low Input Clock Amplitude
Down to 200 mVPP - Package: 9-mm × 9-mm, 64-Pin Quad Flat
No-Lead (QFN) Package
The ADS4229 is a member of the ADS42xx ultralow-power family of dual-channel, 12-bit and 14-bit analog-to-digital converters (ADCs). Innovative design techniques are used to achieve high dynamic performance, while consuming extremely low power with a 1.8-V supply. This topology makes the ADS4229 well-suited for multi-carrier, wide-bandwidth communications applications.
The ADS4229 has gain options that can be used to improve spurious-free dynamic range (SFDR) performance at lower full-scale input ranges. This device also includes a dc offset correction loop that can be used to cancel the ADC offset. Both double data rate (DDR) low-voltage differential signaling (LVDS) and parallel complementary metal oxide semiconductor (CMOS) digital output interfaces are available in a compact QFN-64 PowerPAD™ package.
The device includes internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. The ADS4229 is specified over the industrial temperature range (–40°C to +85°C).
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | ADS4229 Dual-Channel, 12-Bit, 250-MSPS Ultralow-Power ADC datasheet (Rev. C) | PDF | HTML | 2015/5/28 | ||
| * | 使用指南 | Interfacing Altera FPGAs to ADS4249 and DAC3482 (TIDA-00069 Reference Guide) | 2012/7/10 | |||
| 應用說明 | Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) | 2015/5/22 | ||||
| 應用說明 | Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) | 2013/7/19 | ||||
| 應用說明 | High-Speed, Analog-to-Digital Converter Basics | 2012/1/11 | ||||
| 應用說明 | Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A) | 2010/9/10 | ||||
| 應用說明 | Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio | 2009/4/28 | ||||
| 應用說明 | CDCE62005 as Clock Solution for High-Speed ADCs | 2008/9/4 | ||||
| 應用說明 | CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters | 2008/6/8 | ||||
| 應用說明 | Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 | 2008/6/2 | ||||
| 應用說明 | QFN Layout Guidelines | 2006/7/28 |
設計與開發
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| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| VQFN (RGC) | 64 | Ultra Librarian |
訂購與品質
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。