ADS5287
- Speed and Resolution Grades:
- 10-bit, 65MSPS
- Power Dissipation:
- 46mW/Channel at 30MSPS
- 53mW/Channel at 40MSPS
- 62mW/Channel at 50MSPS
- 74mW/Channel at 65MSPS
- 61.7dBFS SNR at 10MHz IF
- Analog Input Full-Scale Range: 2VPP
- Low-Frequency Noise Suppression Mode
- 6dB Overload Recovery in One Clock
- External and Internal (Trimmed) Reference
- 3.3V Analog Supply, 1.8V Digital Supply
- Single-Ended or Differential Clock:
- Clock Duty Cycle Correction Circuit (DCC)
- Programmable Digital Gain: 0dB to 12dB
- Serialized DDR LVDS Output
- Programmable LVDS Current Drive, Internal Termination
- Test Patterns for Enabling Output Capture
- Straight Offset Binary or Two’s Complement Output
- Package Options:
- 9mm × 9mm QFN-64
The ADS5287 is a high-performance, low-power, octal channel analog-to-digital converter (ADC). Available in a 9mm × 9mm QFN package, with serialized low-voltage differential signaling (LVDS) outputs and a wide variety of programmable features, the ADS5287 is highly customizable for a wide range of applications and offers an unprecedented level of system integration. An application note, XAPP774 (available at www.xilinx.com), describes how to interface the serial LVDS outputs of TI’s ADCs to Xilinx field-programmable gate arrays (FPGAs). The ADS5287 is specified over the industrial temperature range of –40°C to +85°C.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | 10-Bit, Octal-Channel ADC Up to 65MSPS. datasheet (Rev. D) | 2012/6/1 | |||
| * | 勘誤表 | Errata to ADS528x, Datasheet Literature Number SBAS397 (Rev. B) | 2007/10/19 | |||
| 應用說明 | Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) | 2015/5/22 | ||||
| 應用說明 | Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) | 2013/7/19 | ||||
| 應用說明 | Understanding Serial LVDS Capture in High-Speed ADCs | 2013/7/10 | ||||
| 應用說明 | Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A) | 2010/9/10 | ||||
| 應用說明 | Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio | 2009/4/28 | ||||
| 應用說明 | CDCE62005 as Clock Solution for High-Speed ADCs | 2008/9/4 | ||||
| 應用說明 | CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters | 2008/6/8 | ||||
| 應用說明 | Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 | 2008/6/2 | ||||
| 使用指南 | ADS528x User's Guide | 2008/1/18 | ||||
| 應用說明 | QFN Layout Guidelines | 2006/7/28 |
設計與開發
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| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| VQFN (RGC) | 64 | Ultra Librarian |