產品詳細資料

Sample rate (max) (Msps) 500 Resolution (Bits) 12 Number of input channels 2 Interface type DDR LVDS Analog input BW (MHz) 1200 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 1 Power consumption (typ) (mW) 1600 Architecture Pipeline SNR (dB) 60.8 ENOB (Bits) 9.8 SFDR (dB) 77 Operating temperature range (°C) -40 to 85 Input buffer No
Sample rate (max) (Msps) 500 Resolution (Bits) 12 Number of input channels 2 Interface type DDR LVDS Analog input BW (MHz) 1200 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 1 Power consumption (typ) (mW) 1600 Architecture Pipeline SNR (dB) 60.8 ENOB (Bits) 9.8 SFDR (dB) 77 Operating temperature range (°C) -40 to 85 Input buffer No
NFBGA (ZAY) 196 144 mm² 12 x 12
  • Dual Channel
  • 12-Bit Resolution
  • Maximum Clock Rate: 500 Msps
  • Low Swing Fullscale Input: 1.0 Vpp
  • Analog Input Buffer with High Impedance Input
  • Input Bandwidth (3 dB): >1.2 GHz
  • Data Output Interface: DDR LVDS
  • 196-Pin BGA Package (12×12mm)
  • Power Dissipation: 910 mW/ch
  • Performance at fin = 230 MHz IF
    • SNR: 60.6 dBFS
    • SFDR: 77 dBc
  • Performance at fin = 700 MHz IF
    • SNR: 59.4 dBFS
    • SFDR: 70 dBc
  • Dual Channel
  • 12-Bit Resolution
  • Maximum Clock Rate: 500 Msps
  • Low Swing Fullscale Input: 1.0 Vpp
  • Analog Input Buffer with High Impedance Input
  • Input Bandwidth (3 dB): >1.2 GHz
  • Data Output Interface: DDR LVDS
  • 196-Pin BGA Package (12×12mm)
  • Power Dissipation: 910 mW/ch
  • Performance at fin = 230 MHz IF
    • SNR: 60.6 dBFS
    • SFDR: 77 dBc
  • Performance at fin = 700 MHz IF
    • SNR: 59.4 dBFS
    • SFDR: 70 dBc

The ADS5404 is a high linearity dual channel 12-bit, 500 MSPS analog-to-digital converter (ADC) easing front end filter design for wide bandwidth receivers. The analog input buffer isolates the internal switching of the on-chip track-and-hold from disturbing the signal source as well as providing a high-impedance input. Optionally the output data can be decimated by two. Designed for high SFDR, the ADC has low-noise performance and outstanding spurious-free dynamic range over a large input-frequency range. The device is available in a 196-pin BGA package and is specified over the full industrial temperature range (–40°C to 85°C).

The ADS5404 is a high linearity dual channel 12-bit, 500 MSPS analog-to-digital converter (ADC) easing front end filter design for wide bandwidth receivers. The analog input buffer isolates the internal switching of the on-chip track-and-hold from disturbing the signal source as well as providing a high-impedance input. Optionally the output data can be decimated by two. Designed for high SFDR, the ADC has low-noise performance and outstanding spurious-free dynamic range over a large input-frequency range. The device is available in a 196-pin BGA package and is specified over the full industrial temperature range (–40°C to 85°C).

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重要文件 類型 標題 格式選項 日期
* Data sheet Dual Channel 12-Bit 500Msps Analog to Digital Converter, ADS5404 datasheet (Rev. B) 2014年 1月 8日
Application note Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) 2015年 5月 22日
Application note Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) 2013年 7月 19日

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ANALOG-ENGINEER-CALC PC software analog engineer's calculator

The analog engineer’s calculator is designed to speed up many of the repetitive calculations that analog circuit design engineers use on a regular basis. This PC-based tool provides a graphical interface with a list of various common calculations ranging from setting operational-amplifier (...)

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NFBGA (ZAY) 196 Ultra Librarian

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