ADS5525
- Maximum Sample Rate: 170 MSPS
- 12-Bit Resolution
- No Missing Codes
- Total Power Dissipation 1.1 W
- Internal Sample and Hold
- 70.5-dBFS SNR at 70-MHz IF
- 84-dBc SFDR at 70-MHz IF
- 11 bits ENOB Minimum at 70-MHz IF
- Double Data Rate (DDR) LVDS and Parallel CMOS Output Options
- Programmable Gain up to 6 dB for SNR/SFDR Trade-Off at High IF
- Reduced Power Modes at Lower Sample Rates
- Supports input clock amplitude down to 400 mVPP
- Clock Duty Cycle Stabilizer
- No External Reference Decoupling Required
- Internal and External Reference Support
- Programmable Output Clock position to ease data capture
- 3.3-V Analog and Digital Supply
- 48-QFN Package (7 mm × 7 mm)
- APPLICATIONS
- Wireless Communications Infrastructure
- Software Defined Radio
- Power Amplifier Linearization
- 802.16d/e
- Test and Measurement Instrumentation
- High Definition Video
- Medical Imaging
- Radar Systems
ADS5525 is a high performance 12-bit, 170-MSPS A/D converter. It offers state-of-the art functionality and performance using advanced techniques to minimize board space. Using an internal sample and hold and low jitter clock buffer, the ADC supports both high SNR and high SFDR at high input frequencies. It features programmable gain options that can be used to improve SFDR performance at lower full-scale analog input ranges.
In a compact 48-pin QFN, the device offers fully differential LVDS DDR (Double Data Rate) interface while parallel CMOS outputs can also be selected. Flexible output clock position programmability is available to ease capture and trade-off setup for hold times. At lower sampling rates, the ADC can be operated at scaled down power with no loss in performance. ADS5525 includes an internal reference, while eliminating the traditional reference pins and associated external decoupling. The device also supports an external reference mode.
The device is specified over the industrial temperature range (-40°C to 85°C).
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | 12-Bit 170 MSPS ADC With DDR LVDS/CMOS Outputs datasheet (Rev. B) | 2007/5/7 | |||
| 應用說明 | Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) | 2015/5/22 | ||||
| 應用說明 | Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) | 2013/7/19 | ||||
| 應用說明 | Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A) | 2010/9/10 | ||||
| 應用說明 | Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio | 2009/4/28 | ||||
| 應用說明 | CDCE62005 as Clock Solution for High-Speed ADCs | 2008/9/4 | ||||
| 應用說明 | CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters | 2008/6/8 | ||||
| 應用說明 | Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 | 2008/6/2 | ||||
| 應用說明 | QFN Layout Guidelines | 2006/7/28 |
設計與開發
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| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| VQFN (RGZ) | 48 | Ultra Librarian |