ADS7229
- 2.7V to 5.5V Analog Supply, Low Power:
- 13.7mW (1MHz, +VA = 3V, +VBD = 1.8V)
- 1MHz Sampling Rate 3V ≤ +VA ≤ 5.5V,
900kHz Sampling Rate 2.7V ≤ +VA ≤ 3V - Excellent DC Performance:
- ±0.15LSB Typ, ±0.5LSB Max INL
- ±0.12LSB Typ, ±0.5LSB Max DNL
- ±0.8mV Max Offset Error at 3V
- ±1.25mV Max Offset Error at 5V
- Excellent AC Performance at fi = 10kHz with 73.9dB SNR, 93.4dB SFDR, -88.5dB THD
- Built-In Conversion Clock (CCLK)
- 1.65V to 5.5V I/O Supply:
- SPI/DSP-Compatible Serial Interface
- SCLK up to 50MHz
- Comprehensive Power-Down Modes:
- Deep Power-Down
- Nap Power-Down
- Auto Nap Power-Down
- Unipolar Input Range: 0V to VREF
- Software Reset
- Global CONVST (Independent of CS)
- Programmable Status/Polarity EOC/INT
- 4 × 4 QFN-16 and TSSOP-16 Packages
- Multi-Chip Daisy-Chain Mode
- Programmable TAG Bit Output
- Auto/Manual Channel Select Mode (ADS7230)
- APPLICATIONS
- Communications
- Transducer Interface
- Medical Instruments
- Magnetometers
- Industrial Process Control
- Data Acquisition Systems
- Automatic Test Equipment
SPI is a trademark of Motorola, Inc.
All other trademarks are the property of their respective owners
The ADS7229 is a low-power, 12-bit, 1MSPS analog-to-digital converter (ADC) with a unipolar input. The device includes a 12-bit capacitor-based successive approximation register (SAR) ADC with inherent sample-and-hold.
The ADS7230 is based on the same core and includes a 2-to-1 input MUX with a programmable TAG bit output option. Both the ADS7229 and ADS7230 offer a high-speed, wide voltage serial interface and are capable of daisy-chain mode operation when multiple converters are used.
These devices are available in 4 × 4 QFN and TSSOP-16 packages, and are fully specified for operation over the industrial -40°C to +85°C temperature range.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | LOW-POWER, 12-BIT, 1MHz, SINGLE/DUAL UNIPOLAR INPUT, ADC w/SERIAL INTERFACE datasheet (Rev. A) | 2009/6/18 | |||
| 電子書 | Best of Baker's Best: Precision Data Converters -- SAR ADCs | 2015/5/21 | ||||
| 應用說明 | Determining Minimum Acquisition Times for SAR ADCs, part 2 | 2011/3/17 | ||||
| 應用說明 | Determining Minimum Acquisition Times for SAR ADCs, part 1 (Rev. A) | 2010/11/10 |
設計與開發
如需其他條款或必要資源,請按一下下方的任何標題以檢視詳細頁面 (如有)。
ANALOG-ENGINEER-CALC — PC software analog engineer's calculator
類比工程師的計算機旨在加速類比電路設計工程師定期使用的許多重複計算。此基於 PC 的工具提供圖形介面,列出各種常見計算,從使用回饋電阻器設定運算放大器增益到選擇適當的電路設計元件以穩定類比數位轉換器 (ADC) 驅動緩衝電路。
除了作為獨立工具使用外,此計算機還與類比工程師口袋參考中描述的概念相得益彰。
ADC-DAC-TO-VREF-SELECT-DESIGN-TOOL — The ADC-TO-VREF-SELECT tool enables the pairing of TI ADCs, DACs, and series voltage references.
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| VQFN (RSA) | 16 | Ultra Librarian |
| TSSOP (PW) | 16 | Ultra Librarian |
訂購與品質
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。