ADS8406
- Pseudo-Bipolar, Fully Differential Input, VREF to VREF
- 16-Bit NMC at 1.25 MSPS
- ±2 LSB INL Max, 1/+1.25 LSB DNL
- 90 dB SNR, -95 dB THD at 100 kHz Input
- Zero Latency
- Internal 4.096 V Reference
- High-Speed Parallel Interface
- Single 5 V Analog Supply
- Wide I/O Supply: 2.7 V to 5.25 V
- Low Power: 155 mW at 1.25 MHz Typ
- Pin Compatible With ADS8412/8402
- 48-Pin TQFP Package
- APPLICATIONS
- DWDM
- Instrumentation
- High-Speed, High-Resolution, Zero Latency Data Acquisition Systems
- Transducer Interface
- Medical Instruments
- Communications
The ADS8406 is a 16-bit, 1.25 MHz A/D converter with an internal 4.096-V reference. The device includes a 16-bit capacitor-based SAR A/D converter with inherent sample and hold. The ADS8406 offers a full 16-bit interface and an 8-bit option where data is read using two 8-bit read cycles.
The ADS8406 has a pseudo-bipolar, fully differential input. It is available in a 48-lead TQFP package and is characterized over the industrial 40°C to 85°C temperature range.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | 16-Bit, 1.25 MSPS, Pseudo-Bipolar Fully Differential Input Micro Power ADC datasheet (Rev. A) | 2004/12/6 | |||
| 白皮書 | Voltage-reference impact on total harmonic distortion | 2016/8/1 | ||||
| 電子書 | Best of Baker's Best: Precision Data Converters -- SAR ADCs | 2015/5/21 | ||||
| 應用說明 | Determining Minimum Acquisition Times for SAR ADCs, part 2 | 2011/3/17 | ||||
| 應用說明 | Determining Minimum Acquisition Times for SAR ADCs, part 1 (Rev. A) | 2010/11/10 |
設計與開發
如需其他條款或必要資源,請按一下下方的任何標題以檢視詳細頁面 (如有)。
ANALOG-ENGINEER-CALC — PC software analog engineer's calculator
類比工程師的計算機旨在加速類比電路設計工程師定期使用的許多重複計算。此基於 PC 的工具提供圖形介面,列出各種常見計算,從使用回饋電阻器設定運算放大器增益到選擇適當的電路設計元件以穩定類比數位轉換器 (ADC) 驅動緩衝電路。
除了作為獨立工具使用外,此計算機還與類比工程師口袋參考中描述的概念相得益彰。
JITTER-SNR-CALC — Jitter and SNR calculator
JITTER-SNR-CALC can be used for calculating theoretical Signal to Noise (SNR) performance of ADCs based on input frequency and clock jitter.
ADC-DAC-TO-VREF-SELECT-DESIGN-TOOL — The ADC-TO-VREF-SELECT tool enables the pairing of TI ADCs, DACs, and series voltage references.
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| TQFP (PFB) | 48 | Ultra Librarian |
訂購與品質
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。