現在提供此產品的更新版本
功能相同,但針腳輸出與所比較的裝置不同。
ADS930
- +3V TO +5V SUPPLY OPERATION
- INTERNAL REFERENCE
- SINGLE-ENDED INPUT RANGE: 1V to 2V
- LOW POWER: 66mW at +3V
- HIGH SNR: 46dB
- LOW DNL: 0.4LSB
- SSOP-28 PACKAGE
- APPLICATIONS
- BATTERY POWERED EQUIPMENT
- CAMCORDERS
- PORTABLE TEST EQUIPMENT
- COMPUTER SCANNERS
- COMMUNICATIONS
The ADS930 is a high speed pipelined Analog-to-Digital Converter (ADC) specified to operate from nominal +3V or +5V power supplies with tolerances of up to 10%. This complete converter includes a high bandwidth track/hold, a 8-bit quantizer and an internal reference.
The ADS930 employs digital error correction techniques to provide excellent differential linearity for demanding imaging applications. Its low distortion and high SNR give the extra margin needed for telecommunications, video and test instrumentation applications.
This high performance ADC is specified for performance at a 30MHz sampling rate. The ADS930 is available in a SSOP-28 package.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | ADS930: SpeedPlus? 8-Bit, 30MHz Sampling Analog-To-Digital Converter datasheet (Rev. A) | 2001/2/23 | |||
| 應用說明 | Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A) | 2010/9/10 | ||||
| 應用說明 | Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio | 2009/4/28 | ||||
| 應用說明 | CDCE62005 as Clock Solution for High-Speed ADCs | 2008/9/4 | ||||
| 應用說明 | CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters | 2008/6/8 | ||||
| 應用說明 | Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 | 2008/6/2 |
設計與開發
如需其他條款或必要資源,請按一下下方的任何標題以檢視詳細頁面 (如有)。
ANALOG-ENGINEER-CALC — PC software analog engineer's calculator
類比工程師的計算機旨在加速類比電路設計工程師定期使用的許多重複計算。此基於 PC 的工具提供圖形介面,列出各種常見計算,從使用回饋電阻器設定運算放大器增益到選擇適當的電路設計元件以穩定類比數位轉換器 (ADC) 驅動緩衝電路。
除了作為獨立工具使用外,此計算機還與類比工程師口袋參考中描述的概念相得益彰。
JITTER-SNR-CALC — Jitter and SNR calculator
JITTER-SNR-CALC can be used for calculating theoretical Signal to Noise (SNR) performance of ADCs based on input frequency and clock jitter.
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| SSOP (DB) | 28 | Ultra Librarian |