CD40106B
- Schmitt-Trigger Inputs
- Hysteresis Voltage
(Typical):
- 0.9 V at VDD = 5 V
- 2.3 V at VDD = 10 V
- 3.5 V at VDD = 15 V
- Noise Immunity Greater Than 50%
- No Limit On Input Rise and Fall Times
- Standardized, Symmetrical Output Characteristics
- For Quiescent Current at 20 V
- Maximum
Input Current Of 1 µA at 18 V Over Full Package Temperature Range:
- 100 nA at 18 V and 25°C
- Low VDD and VSS Current During Slow Input Ramp
- 5-V, 10-V, and 15-V Parametric Ratings
The CD40106B device consists of six Schmitt-Trigger inputs. Each circuit functions as an inverter with Schmitt-Trigger input. The trigger switches at different points for positive- and negative-going signals. The difference between the positive-going voltage (VP) and the negative-going voltages (VN) is defined as hysteresis voltage (VH).
The CD40106B device is supplied in ceramic packaging (J) as well as standard packaging (D, N, NS, PW). All CD40106B devices are rated for –55°C to +125°C ambient temperature operation.
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| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | CD40106B CMOS Hex Schmitt-Trigger Inverters datasheet (Rev. F) | PDF | HTML | 2017/3/9 |
設計與開發
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開發板
14-24-LOGIC-EVM — 適用於 14 針腳至 24 針腳 D、DB、DGV、DW、DYY、NS 和 PW 封裝的邏輯產品通用評估模組
14-24-LOGIC-EVM 評估模組 (EVM) 設計用於支援任何 14 針腳至 24 針腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯裝置。
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| SOIC (D) | 14 | Ultra Librarian |
| TSSOP (PW) | 14 | Ultra Librarian |
| SOP (NS) | 14 | Ultra Librarian |
| PDIP (N) | 14 | Ultra Librarian |